1*7ef62cebSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2d5b0e70fSEmmanuel Vadot%YAML 1.2 3d5b0e70fSEmmanuel Vadot--- 4d5b0e70fSEmmanuel Vadot$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml# 5d5b0e70fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6d5b0e70fSEmmanuel Vadot 7d5b0e70fSEmmanuel Vadottitle: Rockchip RK3228 Clock and Reset Unit (CRU) 8d5b0e70fSEmmanuel Vadot 9d5b0e70fSEmmanuel Vadotmaintainers: 10d5b0e70fSEmmanuel Vadot - Elaine Zhang <zhangqing@rock-chips.com> 11d5b0e70fSEmmanuel Vadot - Heiko Stuebner <heiko@sntech.de> 12d5b0e70fSEmmanuel Vadot 13d5b0e70fSEmmanuel Vadotdescription: | 14d5b0e70fSEmmanuel Vadot The RK3228 clock controller generates and supplies clocks to various 15d5b0e70fSEmmanuel Vadot controllers within the SoC and also implements a reset controller for SoC 16d5b0e70fSEmmanuel Vadot peripherals. 17d5b0e70fSEmmanuel Vadot Each clock is assigned an identifier and client nodes can use this identifier 18d5b0e70fSEmmanuel Vadot to specify the clock which they consume. All available clocks are defined as 19d5b0e70fSEmmanuel Vadot preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be 20d5b0e70fSEmmanuel Vadot used in device tree sources. Similar macros exist for the reset sources in 21d5b0e70fSEmmanuel Vadot these files. 22d5b0e70fSEmmanuel Vadot There are several clocks that are generated outside the SoC. It is expected 23d5b0e70fSEmmanuel Vadot that they are defined using standard clock bindings with following 24d5b0e70fSEmmanuel Vadot clock-output-names: 25d5b0e70fSEmmanuel Vadot - "xin24m" - crystal input - required 26d5b0e70fSEmmanuel Vadot - "ext_i2s" - external I2S clock - optional 27d5b0e70fSEmmanuel Vadot - "ext_gmac" - external GMAC clock - optional 28d5b0e70fSEmmanuel Vadot - "ext_hsadc" - external HSADC clock - optional 29d5b0e70fSEmmanuel Vadot - "phy_50m_out" - output clock of the pll in the mac phy 30d5b0e70fSEmmanuel Vadot 31d5b0e70fSEmmanuel Vadotproperties: 32d5b0e70fSEmmanuel Vadot compatible: 33d5b0e70fSEmmanuel Vadot enum: 34d5b0e70fSEmmanuel Vadot - rockchip,rk3228-cru 35d5b0e70fSEmmanuel Vadot 36d5b0e70fSEmmanuel Vadot reg: 37d5b0e70fSEmmanuel Vadot maxItems: 1 38d5b0e70fSEmmanuel Vadot 39d5b0e70fSEmmanuel Vadot "#clock-cells": 40d5b0e70fSEmmanuel Vadot const: 1 41d5b0e70fSEmmanuel Vadot 42d5b0e70fSEmmanuel Vadot "#reset-cells": 43d5b0e70fSEmmanuel Vadot const: 1 44d5b0e70fSEmmanuel Vadot 45d5b0e70fSEmmanuel Vadot clocks: 46d5b0e70fSEmmanuel Vadot maxItems: 1 47d5b0e70fSEmmanuel Vadot 48d5b0e70fSEmmanuel Vadot clock-names: 49d5b0e70fSEmmanuel Vadot const: xin24m 50d5b0e70fSEmmanuel Vadot 51d5b0e70fSEmmanuel Vadot rockchip,grf: 52d5b0e70fSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/phandle 53d5b0e70fSEmmanuel Vadot description: 54d5b0e70fSEmmanuel Vadot Phandle to the syscon managing the "general register files" (GRF), 55d5b0e70fSEmmanuel Vadot if missing pll rates are not changeable, due to the missing pll 56d5b0e70fSEmmanuel Vadot lock status. 57d5b0e70fSEmmanuel Vadot 58d5b0e70fSEmmanuel Vadotrequired: 59d5b0e70fSEmmanuel Vadot - compatible 60d5b0e70fSEmmanuel Vadot - reg 61d5b0e70fSEmmanuel Vadot - "#clock-cells" 62d5b0e70fSEmmanuel Vadot - "#reset-cells" 63d5b0e70fSEmmanuel Vadot 64d5b0e70fSEmmanuel VadotadditionalProperties: false 65d5b0e70fSEmmanuel Vadot 66d5b0e70fSEmmanuel Vadotexamples: 67d5b0e70fSEmmanuel Vadot - | 68d5b0e70fSEmmanuel Vadot cru: clock-controller@20000000 { 69d5b0e70fSEmmanuel Vadot compatible = "rockchip,rk3228-cru"; 70d5b0e70fSEmmanuel Vadot reg = <0x20000000 0x1000>; 71d5b0e70fSEmmanuel Vadot rockchip,grf = <&grf>; 72d5b0e70fSEmmanuel Vadot #clock-cells = <1>; 73d5b0e70fSEmmanuel Vadot #reset-cells = <1>; 74d5b0e70fSEmmanuel Vadot }; 75