xref: /freebsd/sys/contrib/device-tree/Bindings/clock/renesas,rzg2l-cpg.yaml (revision 3a3af6b2a160bea72509a9d5ef84e25906b0478a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12description: |
13  On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
14  Standby Mode share the same register block.
15
16  They provide the following functionalities:
17    - The CPG block generates various core clocks,
18    - The Module Standby Mode block provides two functions:
19        1. Module Standby, providing a Clock Domain to control the clock supply
20           to individual SoC devices,
21        2. Reset Control, to perform a software reset of individual SoC devices.
22
23properties:
24  compatible:
25    enum:
26      - renesas,r9a07g044-cpg  # RZ/G2{L,LC}
27      - renesas,r9a07g054-cpg  # RZ/V2L
28
29  reg:
30    maxItems: 1
31
32  clocks:
33    maxItems: 1
34
35  clock-names:
36    description:
37      Clock source to CPG can be either from external clock input (EXCLK) or
38      crystal oscillator (XIN/XOUT).
39    const: extal
40
41  '#clock-cells':
42    description: |
43      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
44        and a core clock reference, as defined in
45        <dt-bindings/clock/r9a07g*-cpg.h>
46      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
47        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
48    const: 2
49
50  '#power-domain-cells':
51    description:
52      SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
53      can be power-managed through Module Standby should refer to the CPG device
54      node in their "power-domains" property, as documented by the generic PM
55      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
56    const: 0
57
58  '#reset-cells':
59    description:
60      The single reset specifier cell must be the module number, as defined in
61      the <dt-bindings/clock/r9a07g0*-cpg.h>.
62    const: 1
63
64required:
65  - compatible
66  - reg
67  - clocks
68  - clock-names
69  - '#clock-cells'
70  - '#power-domain-cells'
71  - '#reset-cells'
72
73additionalProperties: false
74
75examples:
76  - |
77    cpg: clock-controller@11010000 {
78            compatible = "renesas,r9a07g044-cpg";
79            reg = <0x11010000 0x10000>;
80            clocks = <&extal_clk>;
81            clock-names = "extal";
82            #clock-cells = <2>;
83            #power-domain-cells = <0>;
84            #reset-cells = <1>;
85    };
86