1* Renesas R9A06G032 SYSCTRL 2 3Required Properties: 4 5 - compatible: Must be: 6 - "renesas,r9a06g032-sysctrl" 7 - reg: Base address and length of the SYSCTRL IO block. 8 - #clock-cells: Must be 1 9 - clocks: References to the parent clocks: 10 - external 40mhz crystal. 11 - external (optional) 32.768khz 12 - external (optional) jtag input 13 - external (optional) RGMII_REFCLK 14 - clock-names: Must be: 15 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; 16 - #power-domain-cells: Must be 0 17 18Examples 19-------- 20 21 - SYSCTRL node: 22 23 sysctrl: system-controller@4000c000 { 24 compatible = "renesas,r9a06g032-sysctrl"; 25 reg = <0x4000c000 0x1000>; 26 #clock-cells = <1>; 27 28 clocks = <&ext_mclk>, <&ext_rtc_clk>, 29 <&ext_jtag_clk>, <&ext_rgmii_ref>; 30 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; 31 #power-domain-cells = <0>; 32 }; 33 34 - Other nodes can use the clocks provided by SYSCTRL as in: 35 36 #include <dt-bindings/clock/r9a06g032-sysctrl.h> 37 uart0: serial@40060000 { 38 compatible = "snps,dw-apb-uart"; 39 reg = <0x40060000 0x400>; 40 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 41 reg-shift = <2>; 42 reg-io-width = <4>; 43 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; 44 clock-names = "baudclk", "apb_pclk"; 45 power-domains = <&sysctrl>; 46 }; 47