1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas Clock Pulse Generator / Module Standby and Software Reset 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12description: | 13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) 14 and MSSR (Module Standby and Software Reset) blocks are intimately connected, 15 and share the same register block. 16 17 They provide the following functionalities: 18 - The CPG block generates various core clocks, 19 - The MSSR block provides two functions: 20 1. Module Standby, providing a Clock Domain to control the clock supply 21 to individual SoC devices, 22 2. Reset Control, to perform a software reset of individual SoC devices. 23 24properties: 25 compatible: 26 enum: 27 - renesas,r7s9210-cpg-mssr # RZ/A2 28 - renesas,r8a7742-cpg-mssr # RZ/G1H 29 - renesas,r8a7743-cpg-mssr # RZ/G1M 30 - renesas,r8a7744-cpg-mssr # RZ/G1N 31 - renesas,r8a7745-cpg-mssr # RZ/G1E 32 - renesas,r8a77470-cpg-mssr # RZ/G1C 33 - renesas,r8a774a1-cpg-mssr # RZ/G2M 34 - renesas,r8a774b1-cpg-mssr # RZ/G2N 35 - renesas,r8a774c0-cpg-mssr # RZ/G2E 36 - renesas,r8a774e1-cpg-mssr # RZ/G2H 37 - renesas,r8a7790-cpg-mssr # R-Car H2 38 - renesas,r8a7791-cpg-mssr # R-Car M2-W 39 - renesas,r8a7792-cpg-mssr # R-Car V2H 40 - renesas,r8a7793-cpg-mssr # R-Car M2-N 41 - renesas,r8a7794-cpg-mssr # R-Car E2 42 - renesas,r8a7795-cpg-mssr # R-Car H3 43 - renesas,r8a7796-cpg-mssr # R-Car M3-W 44 - renesas,r8a77961-cpg-mssr # R-Car M3-W+ 45 - renesas,r8a77965-cpg-mssr # R-Car M3-N 46 - renesas,r8a77970-cpg-mssr # R-Car V3M 47 - renesas,r8a77980-cpg-mssr # R-Car V3H 48 - renesas,r8a77990-cpg-mssr # R-Car E3 49 - renesas,r8a77995-cpg-mssr # R-Car D3 50 - renesas,r8a779a0-cpg-mssr # R-Car V3U 51 - renesas,r8a779f0-cpg-mssr # R-Car S4-8 52 - renesas,r8a779g0-cpg-mssr # R-Car V4H 53 54 reg: 55 maxItems: 1 56 57 clocks: 58 minItems: 1 59 maxItems: 2 60 61 clock-names: 62 minItems: 1 63 maxItems: 2 64 items: 65 enum: 66 - extal # All 67 - extalr # Most R-Car Gen3 and RZ/G2 68 - usb_extal # Most R-Car Gen2 and RZ/G1 69 70 '#clock-cells': 71 description: | 72 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" 73 and a core clock reference, as defined in 74 <dt-bindings/clock/*-cpg-mssr.h> 75 - For module clocks, the two clock specifier cells must be "CPG_MOD" and 76 a module number, as defined in the datasheet. 77 const: 2 78 79 '#power-domain-cells': 80 description: 81 SoC devices that are part of the CPG/MSSR Clock Domain and can be 82 power-managed through Module Standby should refer to the CPG device node 83 in their "power-domains" property, as documented by the generic PM Domain 84 bindings in Documentation/devicetree/bindings/power/power-domain.yaml. 85 const: 0 86 87 '#reset-cells': 88 description: 89 The single reset specifier cell must be the module number, as defined in 90 the datasheet. 91 const: 1 92 93if: 94 not: 95 properties: 96 compatible: 97 items: 98 enum: 99 - renesas,r7s9210-cpg-mssr 100then: 101 required: 102 - '#reset-cells' 103 104required: 105 - compatible 106 - reg 107 - clocks 108 - clock-names 109 - '#clock-cells' 110 - '#power-domain-cells' 111 112additionalProperties: false 113 114examples: 115 - | 116 cpg: clock-controller@e6150000 { 117 compatible = "renesas,r8a7795-cpg-mssr"; 118 reg = <0xe6150000 0x1000>; 119 clocks = <&extal_clk>, <&extalr_clk>; 120 clock-names = "extal", "extalr"; 121 #clock-cells = <2>; 122 #power-domain-cells = <0>; 123 #reset-cells = <1>; 124 }; 125