1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas CPG DIV6 Clock 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12description: 13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse 14 Generator (CPG). Their clock input is divided by a configurable factor from 1 15 to 64. 16 17properties: 18 compatible: 19 items: 20 - enum: 21 - renesas,r8a73a4-div6-clock # R-Mobile APE6 22 - renesas,r8a7740-div6-clock # R-Mobile A1 23 - renesas,sh73a0-div6-clock # SH-Mobile AG5 24 - const: renesas,cpg-div6-clock 25 26 reg: 27 maxItems: 1 28 29 clocks: 30 oneOf: 31 - maxItems: 1 32 - maxItems: 4 33 - maxItems: 8 34 description: 35 For clocks with multiple parents, invalid settings must be specified as 36 "<0>". 37 38 '#clock-cells': 39 const: 0 40 41 clock-output-names: true 42 43required: 44 - compatible 45 - reg 46 - clocks 47 - '#clock-cells' 48 49additionalProperties: false 50 51examples: 52 - | 53 #include <dt-bindings/clock/r8a73a4-clock.h> 54 55 cpg_clocks: cpg_clocks@e6150000 { 56 compatible = "renesas,r8a73a4-cpg-clocks"; 57 reg = <0xe6150000 0x10000>; 58 clocks = <&extal1_clk>, <&extal2_clk>; 59 #clock-cells = <1>; 60 clock-output-names = "main", "pll0", "pll1", "pll2", 61 "pll2s", "pll2h", "z", "z2", 62 "i", "m3", "b", "m1", "m2", 63 "zx", "zs", "hp"; 64 }; 65 66 sdhi2_clk: sdhi2_clk@e615007c { 67 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 68 reg = <0xe615007c 4>; 69 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, 70 <&extal2_clk>; 71 #clock-cells = <0>; 72 }; 73