xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-videocc.yaml (revision 9978553d0199e7ec0bdd1c44fc7f6c7b0c11e43b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Video Clock & Reset Controller on SM8450
8
9maintainers:
10  - Taniya Das <quic_tdas@quicinc.com>
11  - Jagadeesh Kona <quic_jkona@quicinc.com>
12
13description: |
14  Qualcomm video clock control module provides the clocks, resets and power
15  domains on SM8450.
16
17  See also:
18    include/dt-bindings/clock/qcom,sm8450-videocc.h
19    include/dt-bindings/clock/qcom,sm8650-videocc.h
20
21properties:
22  compatible:
23    enum:
24      - qcom,sm8450-videocc
25      - qcom,sm8475-videocc
26      - qcom,sm8550-videocc
27      - qcom,sm8650-videocc
28      - qcom,x1e80100-videocc
29
30  clocks:
31    items:
32      - description: Board XO source
33      - description: Video AHB clock from GCC
34
35  power-domains:
36    description:
37      Power domains required for the clock controller to operate
38    items:
39      - description: MMCX power domain
40      - description: MXC power domain
41
42  required-opps:
43    description:
44      OPP nodes that describe required performance points on power domains
45    items:
46      - description: MMCX performance point
47      - description: MXC performance point
48
49required:
50  - compatible
51  - clocks
52  - power-domains
53  - '#power-domain-cells'
54
55allOf:
56  - $ref: qcom,gcc.yaml#
57  - if:
58      properties:
59        compatible:
60          contains:
61            enum:
62              - qcom,sm8450-videocc
63              - qcom,sm8550-videocc
64    then:
65      required:
66        - required-opps
67
68unevaluatedProperties: false
69
70examples:
71  - |
72    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
73    #include <dt-bindings/clock/qcom,rpmh.h>
74    #include <dt-bindings/power/qcom,rpmhpd.h>
75    videocc: clock-controller@aaf0000 {
76      compatible = "qcom,sm8450-videocc";
77      reg = <0x0aaf0000 0x10000>;
78      clocks = <&rpmhcc RPMH_CXO_CLK>,
79               <&gcc GCC_VIDEO_AHB_CLK>;
80      power-domains = <&rpmhpd RPMHPD_MMCX>,
81                      <&rpmhpd RPMHPD_MXC>;
82      required-opps = <&rpmhpd_opp_low_svs>,
83                      <&rpmhpd_opp_low_svs>;
84      #clock-cells = <1>;
85      #reset-cells = <1>;
86      #power-domain-cells = <1>;
87    };
88...
89