xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,sm8450-gpucc.yaml (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller on SM8450
8
9maintainers:
10  - Konrad Dybcio <konrad.dybcio@linaro.org>
11
12description: |
13  Qualcomm graphics clock control module provides the clocks, resets and power
14  domains on Qualcomm SoCs.
15
16  See also::
17    include/dt-bindings/clock/qcom,sm8450-gpucc.h
18    include/dt-bindings/clock/qcom,sm8550-gpucc.h
19    include/dt-bindings/reset/qcom,sm8450-gpucc.h
20    include/dt-bindings/reset/qcom,sm8650-gpucc.h
21
22properties:
23  compatible:
24    enum:
25      - qcom,sm8450-gpucc
26      - qcom,sm8550-gpucc
27      - qcom,sm8650-gpucc
28
29  clocks:
30    items:
31      - description: Board XO source
32      - description: GPLL0 main branch source
33      - description: GPLL0 div branch source
34
35  '#clock-cells':
36    const: 1
37
38  '#reset-cells':
39    const: 1
40
41  '#power-domain-cells':
42    const: 1
43
44  reg:
45    maxItems: 1
46
47required:
48  - compatible
49  - reg
50  - clocks
51  - '#clock-cells'
52  - '#reset-cells'
53  - '#power-domain-cells'
54
55additionalProperties: false
56
57examples:
58  - |
59    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
60    #include <dt-bindings/clock/qcom,rpmh.h>
61
62    soc {
63        #address-cells = <2>;
64        #size-cells = <2>;
65
66        clock-controller@3d90000 {
67            compatible = "qcom,sm8450-gpucc";
68            reg = <0 0x03d90000 0 0xa000>;
69            clocks = <&rpmhcc RPMH_CXO_CLK>,
70                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
71                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
72            #clock-cells = <1>;
73            #reset-cells = <1>;
74            #power-domain-cells = <1>;
75        };
76    };
77...
78