xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,sm8350-videocc.yaml (revision e0919a4bac2b57a086688ae8ec58058b91f61d86) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8350 Video Clock & Reset Controller
8
9maintainers:
10  - Konrad Dybcio <konrad.dybcio@linaro.org>
11
12description: |
13  Qualcomm video clock control module provides the clocks, resets and power
14  domains on Qualcomm SoCs.
15
16  See also::
17    include/dt-bindings/clock/qcom,videocc-sm8350.h
18    include/dt-bindings/reset/qcom,videocc-sm8350.h
19
20properties:
21  compatible:
22    const: qcom,sm8350-videocc
23
24  clocks:
25    items:
26      - description: Board XO source
27      - description: Board active XO source
28      - description: Board sleep clock
29
30  power-domains:
31    description:
32      A phandle and PM domain specifier for the MMCX power domain.
33    maxItems: 1
34
35  required-opps:
36    description:
37      A phandle to an OPP node describing required MMCX performance point.
38    maxItems: 1
39
40required:
41  - compatible
42  - clocks
43  - power-domains
44  - required-opps
45
46allOf:
47  - $ref: qcom,gcc.yaml#
48
49unevaluatedProperties: false
50
51examples:
52  - |
53    #include <dt-bindings/clock/qcom,rpmh.h>
54    #include <dt-bindings/power/qcom-rpmpd.h>
55
56    clock-controller@abf0000 {
57      compatible = "qcom,sm8350-videocc";
58      reg = <0x0abf0000 0x10000>;
59      clocks = <&rpmhcc RPMH_CXO_CLK>,
60               <&rpmhcc RPMH_CXO_CLK_A>,
61               <&sleep_clk>;
62      power-domains = <&rpmhpd SM8350_MMCX>;
63      required-opps = <&rpmhpd_opp_low_svs>;
64      #clock-cells = <1>;
65      #reset-cells = <1>;
66      #power-domain-cells = <1>;
67    };
68...
69