xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,sm6115-dispcc.yaml (revision a64729f5077d77e13b9497cb33ecb3c82e606ee8) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm6115-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock Controller for SM6115
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11
12description: |
13  Qualcomm display clock control module provides the clocks and power domains
14  on SM6115.
15
16  See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h
17
18properties:
19  compatible:
20    enum:
21      - qcom,sm6115-dispcc
22
23  clocks:
24    items:
25      - description: Board XO source
26      - description: Board sleep clock
27      - description: Byte clock from DSI PHY0
28      - description: Pixel clock from DSI PHY0
29      - description: GPLL0 DISP DIV clock from GCC
30
31  '#clock-cells':
32    const: 1
33
34  '#reset-cells':
35    const: 1
36
37  '#power-domain-cells':
38    const: 1
39
40  reg:
41    maxItems: 1
42
43required:
44  - compatible
45  - reg
46  - clocks
47  - '#clock-cells'
48  - '#reset-cells'
49  - '#power-domain-cells'
50
51additionalProperties: false
52
53examples:
54  - |
55    #include <dt-bindings/clock/qcom,rpmcc.h>
56    #include <dt-bindings/clock/qcom,gcc-sm6115.h>
57    clock-controller@5f00000 {
58      compatible = "qcom,sm6115-dispcc";
59      reg = <0x5f00000 0x20000>;
60      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
61               <&sleep_clk>,
62               <&dsi0_phy 0>,
63               <&dsi0_phy 1>,
64               <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
65      #clock-cells = <1>;
66      #reset-cells = <1>;
67      #power-domain-cells = <1>;
68    };
69...
70