1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Global Clock & Reset Controller on SDX75 8 9maintainers: 10 - Imran Shaik <quic_imrashai@quicinc.com> 11 - Taniya Das <quic_tdas@quicinc.com> 12 13description: | 14 Qualcomm global clock control module provides the clocks, resets and power 15 domains on SDX75 16 17 See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h 18 19properties: 20 compatible: 21 const: qcom,sdx75-gcc 22 23 clocks: 24 items: 25 - description: Board XO source 26 - description: Sleep clock source 27 - description: EMAC0 sgmiiphy mac rclk source 28 - description: EMAC0 sgmiiphy mac tclk source 29 - description: EMAC0 sgmiiphy rclk source 30 - description: EMAC0 sgmiiphy tclk source 31 - description: EMAC1 sgmiiphy mac rclk source 32 - description: EMAC1 sgmiiphy mac tclk source 33 - description: EMAC1 sgmiiphy rclk source 34 - description: EMAC1 sgmiiphy tclk source 35 - description: PCIE20 phy aux clock source 36 - description: PCIE_1 Pipe clock source 37 - description: PCIE_2 Pipe clock source 38 - description: PCIE Pipe clock source 39 - description: USB3 phy wrapper pipe clock source 40 41required: 42 - compatible 43 - clocks 44 45allOf: 46 - $ref: qcom,gcc.yaml# 47 48unevaluatedProperties: false 49 50examples: 51 - | 52 #include <dt-bindings/clock/qcom,rpmh.h> 53 clock-controller@80000 { 54 compatible = "qcom,sdx75-gcc"; 55 reg = <0x80000 0x1f7400>; 56 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>, 57 <&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>, 58 <&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>, 59 <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, 60 <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; 61 #clock-cells = <1>; 62 #reset-cells = <1>; 63 #power-domain-cells = <1>; 64 }; 65... 66