xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,sdm845-gpucc.yaml (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1*c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: GPL-2.0-only
2*c66ec88fSEmmanuel Vadot%YAML 1.2
3*c66ec88fSEmmanuel Vadot---
4*c66ec88fSEmmanuel Vadot$id: http://devicetree.org/schemas/clock/qcom,sdm845-gpucc.yaml#
5*c66ec88fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml#
6*c66ec88fSEmmanuel Vadot
7*c66ec88fSEmmanuel Vadottitle: Qualcomm Graphics Clock & Reset Controller Binding for SDM845
8*c66ec88fSEmmanuel Vadot
9*c66ec88fSEmmanuel Vadotmaintainers:
10*c66ec88fSEmmanuel Vadot  - Taniya Das <tdas@codeaurora.org>
11*c66ec88fSEmmanuel Vadot
12*c66ec88fSEmmanuel Vadotdescription: |
13*c66ec88fSEmmanuel Vadot  Qualcomm graphics clock control module which supports the clocks, resets and
14*c66ec88fSEmmanuel Vadot  power domains on SDM845.
15*c66ec88fSEmmanuel Vadot
16*c66ec88fSEmmanuel Vadot  See also dt-bindings/clock/qcom,gpucc-sdm845.h.
17*c66ec88fSEmmanuel Vadot
18*c66ec88fSEmmanuel Vadotproperties:
19*c66ec88fSEmmanuel Vadot  compatible:
20*c66ec88fSEmmanuel Vadot    const: qcom,sdm845-gpucc
21*c66ec88fSEmmanuel Vadot
22*c66ec88fSEmmanuel Vadot  clocks:
23*c66ec88fSEmmanuel Vadot    items:
24*c66ec88fSEmmanuel Vadot      - description: Board XO source
25*c66ec88fSEmmanuel Vadot      - description: GPLL0 main branch source
26*c66ec88fSEmmanuel Vadot      - description: GPLL0 div branch source
27*c66ec88fSEmmanuel Vadot
28*c66ec88fSEmmanuel Vadot  clock-names:
29*c66ec88fSEmmanuel Vadot    items:
30*c66ec88fSEmmanuel Vadot      - const: bi_tcxo
31*c66ec88fSEmmanuel Vadot      - const: gcc_gpu_gpll0_clk_src
32*c66ec88fSEmmanuel Vadot      - const: gcc_gpu_gpll0_div_clk_src
33*c66ec88fSEmmanuel Vadot
34*c66ec88fSEmmanuel Vadot  '#clock-cells':
35*c66ec88fSEmmanuel Vadot    const: 1
36*c66ec88fSEmmanuel Vadot
37*c66ec88fSEmmanuel Vadot  '#reset-cells':
38*c66ec88fSEmmanuel Vadot    const: 1
39*c66ec88fSEmmanuel Vadot
40*c66ec88fSEmmanuel Vadot  '#power-domain-cells':
41*c66ec88fSEmmanuel Vadot    const: 1
42*c66ec88fSEmmanuel Vadot
43*c66ec88fSEmmanuel Vadot  reg:
44*c66ec88fSEmmanuel Vadot    maxItems: 1
45*c66ec88fSEmmanuel Vadot
46*c66ec88fSEmmanuel Vadotrequired:
47*c66ec88fSEmmanuel Vadot  - compatible
48*c66ec88fSEmmanuel Vadot  - reg
49*c66ec88fSEmmanuel Vadot  - clocks
50*c66ec88fSEmmanuel Vadot  - clock-names
51*c66ec88fSEmmanuel Vadot  - '#clock-cells'
52*c66ec88fSEmmanuel Vadot  - '#reset-cells'
53*c66ec88fSEmmanuel Vadot  - '#power-domain-cells'
54*c66ec88fSEmmanuel Vadot
55*c66ec88fSEmmanuel VadotadditionalProperties: false
56*c66ec88fSEmmanuel Vadot
57*c66ec88fSEmmanuel Vadotexamples:
58*c66ec88fSEmmanuel Vadot  - |
59*c66ec88fSEmmanuel Vadot    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
60*c66ec88fSEmmanuel Vadot    #include <dt-bindings/clock/qcom,rpmh.h>
61*c66ec88fSEmmanuel Vadot    clock-controller@5090000 {
62*c66ec88fSEmmanuel Vadot      compatible = "qcom,sdm845-gpucc";
63*c66ec88fSEmmanuel Vadot      reg = <0x05090000 0x9000>;
64*c66ec88fSEmmanuel Vadot      clocks = <&rpmhcc RPMH_CXO_CLK>,
65*c66ec88fSEmmanuel Vadot               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
66*c66ec88fSEmmanuel Vadot               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
67*c66ec88fSEmmanuel Vadot      clock-names = "bi_tcxo",
68*c66ec88fSEmmanuel Vadot                    "gcc_gpu_gpll0_clk_src",
69*c66ec88fSEmmanuel Vadot                    "gcc_gpu_gpll0_div_clk_src";
70*c66ec88fSEmmanuel Vadot      #clock-cells = <1>;
71*c66ec88fSEmmanuel Vadot      #reset-cells = <1>;
72*c66ec88fSEmmanuel Vadot      #power-domain-cells = <1>;
73*c66ec88fSEmmanuel Vadot    };
74*c66ec88fSEmmanuel Vadot...
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