1*5f62a964SEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*5f62a964SEmmanuel Vadot%YAML 1.2 3*5f62a964SEmmanuel Vadot--- 4*5f62a964SEmmanuel Vadot$id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml# 5*5f62a964SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*5f62a964SEmmanuel Vadot 7*5f62a964SEmmanuel Vadottitle: Qualcomm Display Clock & Reset Controller on SA8775P 8*5f62a964SEmmanuel Vadot 9*5f62a964SEmmanuel Vadotmaintainers: 10*5f62a964SEmmanuel Vadot - Taniya Das <quic_tdas@quicinc.com> 11*5f62a964SEmmanuel Vadot 12*5f62a964SEmmanuel Vadotdescription: | 13*5f62a964SEmmanuel Vadot Qualcomm display clock control module provides the clocks, resets and power 14*5f62a964SEmmanuel Vadot domains on SA8775P. 15*5f62a964SEmmanuel Vadot 16*5f62a964SEmmanuel Vadot See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h 17*5f62a964SEmmanuel Vadot 18*5f62a964SEmmanuel Vadotproperties: 19*5f62a964SEmmanuel Vadot compatible: 20*5f62a964SEmmanuel Vadot enum: 21*5f62a964SEmmanuel Vadot - qcom,sa8775p-dispcc0 22*5f62a964SEmmanuel Vadot - qcom,sa8775p-dispcc1 23*5f62a964SEmmanuel Vadot 24*5f62a964SEmmanuel Vadot clocks: 25*5f62a964SEmmanuel Vadot items: 26*5f62a964SEmmanuel Vadot - description: GCC AHB clock source 27*5f62a964SEmmanuel Vadot - description: Board XO source 28*5f62a964SEmmanuel Vadot - description: Board XO_AO source 29*5f62a964SEmmanuel Vadot - description: Sleep clock source 30*5f62a964SEmmanuel Vadot - description: Link clock from DP0 PHY 31*5f62a964SEmmanuel Vadot - description: VCO DIV clock from DP0 PHY 32*5f62a964SEmmanuel Vadot - description: Link clock from DP1 PHY 33*5f62a964SEmmanuel Vadot - description: VCO DIV clock from DP1 PHY 34*5f62a964SEmmanuel Vadot - description: Byte clock from DSI0 PHY 35*5f62a964SEmmanuel Vadot - description: Pixel clock from DSI0 PHY 36*5f62a964SEmmanuel Vadot - description: Byte clock from DSI1 PHY 37*5f62a964SEmmanuel Vadot - description: Pixel clock from DSI1 PHY 38*5f62a964SEmmanuel Vadot 39*5f62a964SEmmanuel Vadot power-domains: 40*5f62a964SEmmanuel Vadot maxItems: 1 41*5f62a964SEmmanuel Vadot description: MMCX power domain 42*5f62a964SEmmanuel Vadot 43*5f62a964SEmmanuel Vadotrequired: 44*5f62a964SEmmanuel Vadot - compatible 45*5f62a964SEmmanuel Vadot - clocks 46*5f62a964SEmmanuel Vadot - power-domains 47*5f62a964SEmmanuel Vadot - '#power-domain-cells' 48*5f62a964SEmmanuel Vadot 49*5f62a964SEmmanuel VadotallOf: 50*5f62a964SEmmanuel Vadot - $ref: qcom,gcc.yaml# 51*5f62a964SEmmanuel Vadot 52*5f62a964SEmmanuel VadotunevaluatedProperties: false 53*5f62a964SEmmanuel Vadot 54*5f62a964SEmmanuel Vadotexamples: 55*5f62a964SEmmanuel Vadot - | 56*5f62a964SEmmanuel Vadot #include <dt-bindings/clock/qcom,rpmh.h> 57*5f62a964SEmmanuel Vadot #include <dt-bindings/power/qcom-rpmpd.h> 58*5f62a964SEmmanuel Vadot #include <dt-bindings/clock/qcom,sa8775p-gcc.h> 59*5f62a964SEmmanuel Vadot clock-controller@af00000 { 60*5f62a964SEmmanuel Vadot compatible = "qcom,sa8775p-dispcc0"; 61*5f62a964SEmmanuel Vadot reg = <0x0af00000 0x20000>; 62*5f62a964SEmmanuel Vadot clocks = <&gcc GCC_DISP_AHB_CLK>, 63*5f62a964SEmmanuel Vadot <&rpmhcc RPMH_CXO_CLK>, 64*5f62a964SEmmanuel Vadot <&rpmhcc RPMH_CXO_CLK_A>, 65*5f62a964SEmmanuel Vadot <&sleep_clk>, 66*5f62a964SEmmanuel Vadot <&dp_phy0 0>, 67*5f62a964SEmmanuel Vadot <&dp_phy0 1>, 68*5f62a964SEmmanuel Vadot <&dp_phy1 2>, 69*5f62a964SEmmanuel Vadot <&dp_phy1 3>, 70*5f62a964SEmmanuel Vadot <&dsi_phy0 0>, 71*5f62a964SEmmanuel Vadot <&dsi_phy0 1>, 72*5f62a964SEmmanuel Vadot <&dsi_phy1 2>, 73*5f62a964SEmmanuel Vadot <&dsi_phy1 3>; 74*5f62a964SEmmanuel Vadot power-domains = <&rpmhpd SA8775P_MMCX>; 75*5f62a964SEmmanuel Vadot #clock-cells = <1>; 76*5f62a964SEmmanuel Vadot #reset-cells = <1>; 77*5f62a964SEmmanuel Vadot #power-domain-cells = <1>; 78*5f62a964SEmmanuel Vadot }; 79*5f62a964SEmmanuel Vadot... 80