1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Multimedia Clock & Reset Controller 8 9maintainers: 10 - Jeffrey Hugo <quic_jhugo@quicinc.com> 11 - Taniya Das <tdas@codeaurora.org> 12 13description: | 14 Qualcomm multimedia clock control module provides the clocks, resets and 15 power domains. 16 17properties: 18 compatible: 19 enum: 20 - qcom,mmcc-apq8064 21 - qcom,mmcc-apq8084 22 - qcom,mmcc-msm8226 23 - qcom,mmcc-msm8660 24 - qcom,mmcc-msm8960 25 - qcom,mmcc-msm8974 26 - qcom,mmcc-msm8992 27 - qcom,mmcc-msm8994 28 - qcom,mmcc-msm8996 29 - qcom,mmcc-msm8998 30 - qcom,mmcc-sdm630 31 - qcom,mmcc-sdm660 32 33 clocks: 34 minItems: 8 35 maxItems: 13 36 37 clock-names: 38 minItems: 8 39 maxItems: 13 40 41 '#clock-cells': 42 const: 1 43 44 '#reset-cells': 45 const: 1 46 47 '#power-domain-cells': 48 const: 1 49 50 reg: 51 maxItems: 1 52 53 protected-clocks: 54 description: 55 Protected clock specifier list as per common clock binding 56 57 vdd-gfx-supply: 58 description: 59 Regulator supply for the GPU_GX GDSC 60 61required: 62 - compatible 63 - reg 64 - '#clock-cells' 65 - '#reset-cells' 66 - '#power-domain-cells' 67 68additionalProperties: false 69 70allOf: 71 - if: 72 properties: 73 compatible: 74 contains: 75 enum: 76 - qcom,mmcc-apq8064 77 - qcom,mmcc-msm8960 78 then: 79 properties: 80 clocks: 81 items: 82 - description: Board PXO source 83 - description: PLL 3 clock 84 - description: PLL 3 Vote clock 85 - description: DSI phy instance 1 dsi clock 86 - description: DSI phy instance 1 byte clock 87 - description: DSI phy instance 2 dsi clock 88 - description: DSI phy instance 2 byte clock 89 - description: HDMI phy PLL clock 90 91 clock-names: 92 items: 93 - const: pxo 94 - const: pll3 95 - const: pll8_vote 96 - const: dsi1pll 97 - const: dsi1pllbyte 98 - const: dsi2pll 99 - const: dsi2pllbyte 100 - const: hdmipll 101 102 - if: 103 properties: 104 compatible: 105 contains: 106 enum: 107 - qcom,mmcc-msm8974 108 then: 109 properties: 110 clocks: 111 items: 112 - description: Board XO source 113 - description: MMSS GPLL0 voted clock 114 - description: GPLL0 voted clock 115 - description: GPLL1 voted clock 116 - description: GFX3D clock source 117 - description: DSI phy instance 0 dsi clock 118 - description: DSI phy instance 0 byte clock 119 - description: DSI phy instance 1 dsi clock 120 - description: DSI phy instance 1 byte clock 121 - description: HDMI phy PLL clock 122 - description: eDP phy PLL link clock 123 - description: eDP phy PLL vco clock 124 125 clock-names: 126 items: 127 - const: xo 128 - const: mmss_gpll0_vote 129 - const: gpll0_vote 130 - const: gpll1_vote 131 - const: gfx3d_clk_src 132 - const: dsi0pll 133 - const: dsi0pllbyte 134 - const: dsi1pll 135 - const: dsi1pllbyte 136 - const: hdmipll 137 - const: edp_link_clk 138 - const: edp_vco_div 139 140 - if: 141 properties: 142 compatible: 143 contains: 144 enum: 145 - qcom,mmcc-apq8084 146 then: 147 properties: 148 clocks: 149 items: 150 - description: Board XO source 151 - description: Board sleep source 152 - description: MMSS GPLL0 voted clock 153 - description: GPLL0 clock 154 - description: GPLL0 voted clock 155 - description: GPLL1 clock 156 - description: DSI phy instance 0 dsi clock 157 - description: DSI phy instance 0 byte clock 158 - description: DSI phy instance 1 dsi clock 159 - description: DSI phy instance 1 byte clock 160 - description: HDMI phy PLL clock 161 - description: eDP phy PLL link clock 162 - description: eDP phy PLL vco clock 163 164 clock-names: 165 items: 166 - const: xo 167 - const: sleep_clk 168 - const: mmss_gpll0_vote 169 - const: gpll0 170 - const: gpll0_vote 171 - const: gpll1 172 - const: dsi0pll 173 - const: dsi0pllbyte 174 - const: dsi1pll 175 - const: dsi1pllbyte 176 - const: hdmipll 177 - const: edp_link_clk 178 - const: edp_vco_div 179 180 - if: 181 properties: 182 compatible: 183 contains: 184 enum: 185 - qcom,mmcc-msm8994 186 - qcom,mmcc-msm8998 187 - qcom,mmcc-sdm630 188 - qcom,mmcc-sdm660 189 then: 190 required: 191 - clocks 192 - clock-names 193 194 - if: 195 properties: 196 compatible: 197 contains: 198 const: qcom,mmcc-msm8994 199 then: 200 properties: 201 clocks: 202 items: 203 - description: Board XO source 204 - description: Global PLL 0 clock 205 - description: MMSS NoC AHB clock 206 - description: GFX3D clock 207 - description: DSI phy instance 0 dsi clock 208 - description: DSI phy instance 0 byte clock 209 - description: DSI phy instance 1 dsi clock 210 - description: DSI phy instance 1 byte clock 211 - description: HDMI phy PLL clock 212 213 clock-names: 214 items: 215 - const: xo 216 - const: gpll0 217 - const: mmssnoc_ahb 218 - const: oxili_gfx3d_clk_src 219 - const: dsi0pll 220 - const: dsi0pllbyte 221 - const: dsi1pll 222 - const: dsi1pllbyte 223 - const: hdmipll 224 225 - if: 226 properties: 227 compatible: 228 contains: 229 const: qcom,mmcc-msm8996 230 then: 231 properties: 232 clocks: 233 items: 234 - description: Board XO source 235 - description: Global PLL 0 clock 236 - description: MMSS NoC AHB clock 237 - description: DSI phy instance 0 dsi clock 238 - description: DSI phy instance 0 byte clock 239 - description: DSI phy instance 1 dsi clock 240 - description: DSI phy instance 1 byte clock 241 - description: HDMI phy PLL clock 242 243 clock-names: 244 items: 245 - const: xo 246 - const: gpll0 247 - const: gcc_mmss_noc_cfg_ahb_clk 248 - const: dsi0pll 249 - const: dsi0pllbyte 250 - const: dsi1pll 251 - const: dsi1pllbyte 252 - const: hdmipll 253 254 - if: 255 properties: 256 compatible: 257 contains: 258 const: qcom,mmcc-msm8998 259 then: 260 properties: 261 clocks: 262 items: 263 - description: Board XO source 264 - description: Global PLL 0 clock 265 - description: DSI phy instance 0 dsi clock 266 - description: DSI phy instance 0 byte clock 267 - description: DSI phy instance 1 dsi clock 268 - description: DSI phy instance 1 byte clock 269 - description: HDMI phy PLL clock 270 - description: DisplayPort phy PLL link clock 271 - description: DisplayPort phy PLL vco clock 272 273 clock-names: 274 items: 275 - const: xo 276 - const: gpll0 277 - const: dsi0dsi 278 - const: dsi0byte 279 - const: dsi1dsi 280 - const: dsi1byte 281 - const: hdmipll 282 - const: dplink 283 - const: dpvco 284 285 - if: 286 properties: 287 compatible: 288 contains: 289 enum: 290 - qcom,mmcc-sdm630 291 - qcom,mmcc-sdm660 292 then: 293 properties: 294 clocks: 295 items: 296 - description: Board XO source 297 - description: Board sleep source 298 - description: Global PLL 0 clock 299 - description: Global PLL 0 DIV clock 300 - description: DSI phy instance 0 dsi clock 301 - description: DSI phy instance 0 byte clock 302 - description: DSI phy instance 1 dsi clock 303 - description: DSI phy instance 1 byte clock 304 - description: DisplayPort phy PLL link clock 305 - description: DisplayPort phy PLL vco clock 306 307 clock-names: 308 items: 309 - const: xo 310 - const: sleep_clk 311 - const: gpll0 312 - const: gpll0_div 313 - const: dsi0pll 314 - const: dsi0pllbyte 315 - const: dsi1pll 316 - const: dsi1pllbyte 317 - const: dp_link_2x_clk_divsel_five 318 - const: dp_vco_divided_clk_src_mux 319 320examples: 321 # Example for MMCC for MSM8960: 322 - | 323 clock-controller@4000000 { 324 compatible = "qcom,mmcc-msm8960"; 325 reg = <0x4000000 0x1000>; 326 #clock-cells = <1>; 327 #reset-cells = <1>; 328 #power-domain-cells = <1>; 329 }; 330... 331