xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,ipq9574-gcc.yaml (revision 02e9120893770924227138ba49df1edb3896112a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on IPQ9574
8
9maintainers:
10  - Anusha Rao <quic_anusha@quicinc.com>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on IPQ9574
15
16  See also::
17    include/dt-bindings/clock/qcom,ipq9574-gcc.h
18    include/dt-bindings/reset/qcom,ipq9574-gcc.h
19
20properties:
21  compatible:
22    const: qcom,ipq9574-gcc
23
24  clocks:
25    items:
26      - description: Board XO source
27      - description: Sleep clock source
28      - description: Bias PLL ubi clock source
29      - description: PCIE30 PHY0 pipe clock source
30      - description: PCIE30 PHY1 pipe clock source
31      - description: PCIE30 PHY2 pipe clock source
32      - description: PCIE30 PHY3 pipe clock source
33      - description: USB3 PHY pipe clock source
34
35required:
36  - compatible
37  - clocks
38
39allOf:
40  - $ref: qcom,gcc.yaml#
41
42unevaluatedProperties: false
43
44examples:
45  - |
46    clock-controller@1800000 {
47      compatible = "qcom,ipq9574-gcc";
48      reg = <0x01800000 0x80000>;
49      clocks = <&xo_board_clk>,
50               <&sleep_clk>,
51               <&bias_pll_ubi_nc_clk>,
52               <&pcie30_phy0_pipe_clk>,
53               <&pcie30_phy1_pipe_clk>,
54               <&pcie30_phy2_pipe_clk>,
55               <&pcie30_phy3_pipe_clk>,
56               <&usb3phy_0_cc_pipe_clk>;
57      #clock-cells = <1>;
58      #reset-cells = <1>;
59      #power-domain-cells = <1>;
60    };
61...
62