1High-Frequency PLL (HFPLL) 2 3PROPERTIES 4 5- compatible: 6 Usage: required 7 Value type: <string>: 8 shall contain only one of the following. The generic 9 compatible "qcom,hfpll" should be also included. 10 11 "qcom,hfpll-ipq8064", "qcom,hfpll" 12 "qcom,hfpll-apq8064", "qcom,hfpll" 13 "qcom,hfpll-msm8974", "qcom,hfpll" 14 "qcom,hfpll-msm8960", "qcom,hfpll" 15 16- reg: 17 Usage: required 18 Value type: <prop-encoded-array> 19 Definition: address and size of HPLL registers. An optional second 20 element specifies the address and size of the alias 21 register region. 22 23- clocks: 24 Usage: required 25 Value type: <prop-encoded-array> 26 Definition: reference to the xo clock. 27 28- clock-names: 29 Usage: required 30 Value type: <stringlist> 31 Definition: must be "xo". 32 33- clock-output-names: 34 Usage: required 35 Value type: <string> 36 Definition: Name of the PLL. Typically hfpllX where X is a CPU number 37 starting at 0. Otherwise hfpll_Y where Y is more specific 38 such as "l2". 39 40Example: 41 421) An HFPLL for the L2 cache. 43 44 clock-controller@f9016000 { 45 compatible = "qcom,hfpll-ipq8064", "qcom,hfpll"; 46 reg = <0xf9016000 0x30>; 47 clocks = <&xo_board>; 48 clock-names = "xo"; 49 clock-output-names = "hfpll_l2"; 50 }; 51 522) An HFPLL for CPU0. This HFPLL has the alias register region. 53 54 clock-controller@f908a000 { 55 compatible = "qcom,hfpll-ipq8064", "qcom,hfpll"; 56 reg = <0xf908a000 0x30>, <0xf900a000 0x30>; 57 clocks = <&xo_board>; 58 clock-names = "xo"; 59 clock-output-names = "hfpll0"; 60 }; 61