xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,gpucc.yaml (revision e1c4c8dd8d2d10b6104f06856a77bd5b4813a801) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller
8
9maintainers:
10  - Taniya Das <tdas@codeaurora.org>
11
12description: |
13  Qualcomm graphics clock control module provides the clocks, resets and power
14  domains on Qualcomm SoCs.
15
16  See also::
17    include/dt-bindings/clock/qcom,gpucc-sdm845.h
18    include/dt-bindings/clock/qcom,gpucc-sa8775p.h
19    include/dt-bindings/clock/qcom,gpucc-sc7180.h
20    include/dt-bindings/clock/qcom,gpucc-sc7280.h
21    include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
22    include/dt-bindings/clock/qcom,gpucc-sm6350.h
23    include/dt-bindings/clock/qcom,gpucc-sm8150.h
24    include/dt-bindings/clock/qcom,gpucc-sm8250.h
25    include/dt-bindings/clock/qcom,gpucc-sm8350.h
26
27properties:
28  compatible:
29    enum:
30      - qcom,sdm845-gpucc
31      - qcom,sa8775p-gpucc
32      - qcom,sc7180-gpucc
33      - qcom,sc7280-gpucc
34      - qcom,sc8180x-gpucc
35      - qcom,sc8280xp-gpucc
36      - qcom,sm6350-gpucc
37      - qcom,sm8150-gpucc
38      - qcom,sm8250-gpucc
39      - qcom,sm8350-gpucc
40
41  clocks:
42    items:
43      - description: Board XO source
44      - description: GPLL0 main branch source
45      - description: GPLL0 div branch source
46
47  clock-names:
48    items:
49      - const: bi_tcxo
50      - const: gcc_gpu_gpll0_clk_src
51      - const: gcc_gpu_gpll0_div_clk_src
52
53  power-domains:
54    maxItems: 1
55
56  '#clock-cells':
57    const: 1
58
59  '#reset-cells':
60    const: 1
61
62  '#power-domain-cells':
63    const: 1
64
65  reg:
66    maxItems: 1
67
68required:
69  - compatible
70  - reg
71  - clocks
72  - clock-names
73  - '#clock-cells'
74  - '#reset-cells'
75  - '#power-domain-cells'
76
77additionalProperties: false
78
79examples:
80  - |
81    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
82    #include <dt-bindings/clock/qcom,rpmh.h>
83    clock-controller@5090000 {
84      compatible = "qcom,sdm845-gpucc";
85      reg = <0x05090000 0x9000>;
86      clocks = <&rpmhcc RPMH_CXO_CLK>,
87               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
88               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
89      clock-names = "bi_tcxo",
90                    "gcc_gpu_gpll0_clk_src",
91                    "gcc_gpu_gpll0_div_clk_src";
92      #clock-cells = <1>;
93      #reset-cells = <1>;
94      #power-domain-cells = <1>;
95    };
96...
97