xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm8x50.yaml (revision c7046f76c2c027b00c0e6ba57cfd28f1a78f5e23) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
8
9maintainers:
10  - Jonathan Marek <jonathan@marek.ca>
11
12description: |
13  Qualcomm display clock control module which supports the clocks, resets and
14  power domains on SM8150 and SM8250.
15
16  See also:
17    dt-bindings/clock/qcom,dispcc-sm8150.h
18    dt-bindings/clock/qcom,dispcc-sm8250.h
19
20properties:
21  compatible:
22    enum:
23      - qcom,sc8180x-dispcc
24      - qcom,sm8150-dispcc
25      - qcom,sm8250-dispcc
26
27  clocks:
28    items:
29      - description: Board XO source
30      - description: Byte clock from DSI PHY0
31      - description: Pixel clock from DSI PHY0
32      - description: Byte clock from DSI PHY1
33      - description: Pixel clock from DSI PHY1
34      - description: Link clock from DP PHY
35      - description: VCO DIV clock from DP PHY
36
37  clock-names:
38    items:
39      - const: bi_tcxo
40      - const: dsi0_phy_pll_out_byteclk
41      - const: dsi0_phy_pll_out_dsiclk
42      - const: dsi1_phy_pll_out_byteclk
43      - const: dsi1_phy_pll_out_dsiclk
44      - const: dp_phy_pll_link_clk
45      - const: dp_phy_pll_vco_div_clk
46
47  '#clock-cells':
48    const: 1
49
50  '#reset-cells':
51    const: 1
52
53  '#power-domain-cells':
54    const: 1
55
56  reg:
57    maxItems: 1
58
59  power-domains:
60    description:
61      A phandle and PM domain specifier for the MMCX power domain.
62    maxItems: 1
63
64  required-opps:
65    description:
66      A phandle to an OPP node describing required MMCX performance point.
67    maxItems: 1
68
69required:
70  - compatible
71  - reg
72  - clocks
73  - clock-names
74  - '#clock-cells'
75  - '#reset-cells'
76  - '#power-domain-cells'
77
78additionalProperties: false
79
80examples:
81  - |
82    #include <dt-bindings/clock/qcom,rpmh.h>
83    #include <dt-bindings/power/qcom-rpmpd.h>
84    clock-controller@af00000 {
85      compatible = "qcom,sm8250-dispcc";
86      reg = <0x0af00000 0x10000>;
87      clocks = <&rpmhcc RPMH_CXO_CLK>,
88               <&dsi0_phy 0>,
89               <&dsi0_phy 1>,
90               <&dsi1_phy 0>,
91               <&dsi1_phy 1>,
92               <&dp_phy 0>,
93               <&dp_phy 1>;
94      clock-names = "bi_tcxo",
95                    "dsi0_phy_pll_out_byteclk",
96                    "dsi0_phy_pll_out_dsiclk",
97                    "dsi1_phy_pll_out_byteclk",
98                    "dsi1_phy_pll_out_dsiclk",
99                    "dp_phy_pll_link_clk",
100                    "dp_phy_pll_vco_div_clk";
101      #clock-cells = <1>;
102      #reset-cells = <1>;
103      #power-domain-cells = <1>;
104      power-domains = <&rpmhpd SM8250_MMCX>;
105      required-opps = <&rpmhpd_opp_low_svs>;
106    };
107...
108