xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm8x50.yaml (revision b077aed33b7b6aefca7b17ddb250cf521f938613) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
8
9maintainers:
10  - Jonathan Marek <jonathan@marek.ca>
11
12description: |
13  Qualcomm display clock control module which supports the clocks, resets and
14  power domains on SM8150/SM8250/SM8350.
15
16  See also:
17    dt-bindings/clock/qcom,dispcc-sm8150.h
18    dt-bindings/clock/qcom,dispcc-sm8250.h
19    dt-bindings/clock/qcom,dispcc-sm8350.h
20
21properties:
22  compatible:
23    enum:
24      - qcom,sc8180x-dispcc
25      - qcom,sm8150-dispcc
26      - qcom,sm8250-dispcc
27      - qcom,sm8350-dispcc
28
29  clocks:
30    items:
31      - description: Board XO source
32      - description: Byte clock from DSI PHY0
33      - description: Pixel clock from DSI PHY0
34      - description: Byte clock from DSI PHY1
35      - description: Pixel clock from DSI PHY1
36      - description: Link clock from DP PHY
37      - description: VCO DIV clock from DP PHY
38
39  clock-names:
40    items:
41      - const: bi_tcxo
42      - const: dsi0_phy_pll_out_byteclk
43      - const: dsi0_phy_pll_out_dsiclk
44      - const: dsi1_phy_pll_out_byteclk
45      - const: dsi1_phy_pll_out_dsiclk
46      - const: dp_phy_pll_link_clk
47      - const: dp_phy_pll_vco_div_clk
48
49  '#clock-cells':
50    const: 1
51
52  '#reset-cells':
53    const: 1
54
55  '#power-domain-cells':
56    const: 1
57
58  reg:
59    maxItems: 1
60
61  power-domains:
62    description:
63      A phandle and PM domain specifier for the MMCX power domain.
64    maxItems: 1
65
66  required-opps:
67    description:
68      A phandle to an OPP node describing required MMCX performance point.
69    maxItems: 1
70
71required:
72  - compatible
73  - reg
74  - clocks
75  - clock-names
76  - '#clock-cells'
77  - '#reset-cells'
78  - '#power-domain-cells'
79
80additionalProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/clock/qcom,rpmh.h>
85    #include <dt-bindings/power/qcom-rpmpd.h>
86    clock-controller@af00000 {
87      compatible = "qcom,sm8250-dispcc";
88      reg = <0x0af00000 0x10000>;
89      clocks = <&rpmhcc RPMH_CXO_CLK>,
90               <&dsi0_phy 0>,
91               <&dsi0_phy 1>,
92               <&dsi1_phy 0>,
93               <&dsi1_phy 1>,
94               <&dp_phy 0>,
95               <&dp_phy 1>;
96      clock-names = "bi_tcxo",
97                    "dsi0_phy_pll_out_byteclk",
98                    "dsi0_phy_pll_out_dsiclk",
99                    "dsi1_phy_pll_out_byteclk",
100                    "dsi1_phy_pll_out_dsiclk",
101                    "dp_phy_pll_link_clk",
102                    "dp_phy_pll_vco_div_clk";
103      #clock-cells = <1>;
104      #reset-cells = <1>;
105      #power-domain-cells = <1>;
106      power-domains = <&rpmhpd SM8250_MMCX>;
107      required-opps = <&rpmhpd_opp_low_svs>;
108    };
109...
110