xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm8x50.yaml (revision 3ff01b231dfa83d518854c63e7c9cd1debd1139e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
8
9maintainers:
10  - Jonathan Marek <jonathan@marek.ca>
11
12description: |
13  Qualcomm display clock control module which supports the clocks, resets and
14  power domains on SM8150 and SM8250.
15
16  See also:
17    dt-bindings/clock/qcom,dispcc-sm8150.h
18    dt-bindings/clock/qcom,dispcc-sm8250.h
19
20properties:
21  compatible:
22    enum:
23      - qcom,sm8150-dispcc
24      - qcom,sm8250-dispcc
25
26  clocks:
27    items:
28      - description: Board XO source
29      - description: Byte clock from DSI PHY0
30      - description: Pixel clock from DSI PHY0
31      - description: Byte clock from DSI PHY1
32      - description: Pixel clock from DSI PHY1
33      - description: Link clock from DP PHY
34      - description: VCO DIV clock from DP PHY
35
36  clock-names:
37    items:
38      - const: bi_tcxo
39      - const: dsi0_phy_pll_out_byteclk
40      - const: dsi0_phy_pll_out_dsiclk
41      - const: dsi1_phy_pll_out_byteclk
42      - const: dsi1_phy_pll_out_dsiclk
43      - const: dp_phy_pll_link_clk
44      - const: dp_phy_pll_vco_div_clk
45
46  '#clock-cells':
47    const: 1
48
49  '#reset-cells':
50    const: 1
51
52  '#power-domain-cells':
53    const: 1
54
55  reg:
56    maxItems: 1
57
58required:
59  - compatible
60  - reg
61  - clocks
62  - clock-names
63  - '#clock-cells'
64  - '#reset-cells'
65  - '#power-domain-cells'
66
67additionalProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/clock/qcom,rpmh.h>
72    clock-controller@af00000 {
73      compatible = "qcom,sm8250-dispcc";
74      reg = <0x0af00000 0x10000>;
75      clocks = <&rpmhcc RPMH_CXO_CLK>,
76               <&dsi0_phy 0>,
77               <&dsi0_phy 1>,
78               <&dsi1_phy 0>,
79               <&dsi1_phy 1>,
80               <&dp_phy 0>,
81               <&dp_phy 1>;
82      clock-names = "bi_tcxo",
83                    "dsi0_phy_pll_out_byteclk",
84                    "dsi0_phy_pll_out_dsiclk",
85                    "dsi1_phy_pll_out_byteclk",
86                    "dsi1_phy_pll_out_dsiclk",
87                    "dp_phy_pll_link_clk",
88                    "dp_phy_pll_vco_div_clk";
89      #clock-cells = <1>;
90      #reset-cells = <1>;
91      #power-domain-cells = <1>;
92    };
93...
94