xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qcom,gpucc.yaml (revision cb7aa33ac6cd46a5434798e50363136e64f3ae98) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller
8
9maintainers:
10  - Taniya Das <tdas@codeaurora.org>
11
12description: |
13  Qualcomm graphics clock control module provides the clocks, resets and power
14  domains on Qualcomm SoCs.
15
16  See also::
17    include/dt-bindings/clock/qcom,gpucc-sdm845.h
18    include/dt-bindings/clock/qcom,gpucc-sc7180.h
19    include/dt-bindings/clock/qcom,gpucc-sc7280.h
20    include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
21    include/dt-bindings/clock/qcom,gpucc-sm6350.h
22    include/dt-bindings/clock/qcom,gpucc-sm8150.h
23    include/dt-bindings/clock/qcom,gpucc-sm8250.h
24    include/dt-bindings/clock/qcom,gpucc-sm8350.h
25
26properties:
27  compatible:
28    enum:
29      - qcom,sdm845-gpucc
30      - qcom,sc7180-gpucc
31      - qcom,sc7280-gpucc
32      - qcom,sc8180x-gpucc
33      - qcom,sc8280xp-gpucc
34      - qcom,sm6350-gpucc
35      - qcom,sm8150-gpucc
36      - qcom,sm8250-gpucc
37      - qcom,sm8350-gpucc
38
39  clocks:
40    items:
41      - description: Board XO source
42      - description: GPLL0 main branch source
43      - description: GPLL0 div branch source
44
45  clock-names:
46    items:
47      - const: bi_tcxo
48      - const: gcc_gpu_gpll0_clk_src
49      - const: gcc_gpu_gpll0_div_clk_src
50
51  '#clock-cells':
52    const: 1
53
54  '#reset-cells':
55    const: 1
56
57  '#power-domain-cells':
58    const: 1
59
60  reg:
61    maxItems: 1
62
63required:
64  - compatible
65  - reg
66  - clocks
67  - clock-names
68  - '#clock-cells'
69  - '#reset-cells'
70  - '#power-domain-cells'
71
72additionalProperties: false
73
74examples:
75  - |
76    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
77    #include <dt-bindings/clock/qcom,rpmh.h>
78    clock-controller@5090000 {
79      compatible = "qcom,sdm845-gpucc";
80      reg = <0x05090000 0x9000>;
81      clocks = <&rpmhcc RPMH_CXO_CLK>,
82               <&gcc GCC_GPU_GPLL0_CLK_SRC>,
83               <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
84      clock-names = "bi_tcxo",
85                    "gcc_gpu_gpll0_clk_src",
86                    "gcc_gpu_gpll0_div_clk_src";
87      #clock-cells = <1>;
88      #reset-cells = <1>;
89      #power-domain-cells = <1>;
90    };
91...
92