xref: /freebsd/sys/contrib/device-tree/Bindings/clock/qca,ath79-pll.yaml (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa)
1*833e5d42SEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*833e5d42SEmmanuel Vadot%YAML 1.2
3*833e5d42SEmmanuel Vadot---
4*833e5d42SEmmanuel Vadot$id: http://devicetree.org/schemas/clock/qca,ath79-pll.yaml#
5*833e5d42SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml#
6*833e5d42SEmmanuel Vadot
7*833e5d42SEmmanuel Vadottitle: Qualcomm Atheros ATH79 PLL controller
8*833e5d42SEmmanuel Vadot
9*833e5d42SEmmanuel Vadotmaintainers:
10*833e5d42SEmmanuel Vadot  - Alban Bedel <albeu@free.fr>
11*833e5d42SEmmanuel Vadot  - Antony Pavlov <antonynpavlov@gmail.com>
12*833e5d42SEmmanuel Vadot
13*833e5d42SEmmanuel Vadotdescription: >
14*833e5d42SEmmanuel Vadot  The PLL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
15*833e5d42SEmmanuel Vadot
16*833e5d42SEmmanuel Vadotproperties:
17*833e5d42SEmmanuel Vadot  compatible:
18*833e5d42SEmmanuel Vadot    oneOf:
19*833e5d42SEmmanuel Vadot      - items:
20*833e5d42SEmmanuel Vadot          - const: qca,ar9132-pll
21*833e5d42SEmmanuel Vadot          - const: qca,ar9130-pll
22*833e5d42SEmmanuel Vadot      - items:
23*833e5d42SEmmanuel Vadot          - enum:
24*833e5d42SEmmanuel Vadot              - qca,ar7100-pll
25*833e5d42SEmmanuel Vadot              - qca,ar7240-pll
26*833e5d42SEmmanuel Vadot              - qca,ar9130-pll
27*833e5d42SEmmanuel Vadot              - qca,ar9330-pll
28*833e5d42SEmmanuel Vadot              - qca,ar9340-pll
29*833e5d42SEmmanuel Vadot              - qca,qca9530-pll
30*833e5d42SEmmanuel Vadot              - qca,qca9550-pll
31*833e5d42SEmmanuel Vadot              - qca,qca9560-pll
32*833e5d42SEmmanuel Vadot
33*833e5d42SEmmanuel Vadot  reg:
34*833e5d42SEmmanuel Vadot    maxItems: 1
35*833e5d42SEmmanuel Vadot
36*833e5d42SEmmanuel Vadot  clock-names:
37*833e5d42SEmmanuel Vadot    items:
38*833e5d42SEmmanuel Vadot      - const: ref
39*833e5d42SEmmanuel Vadot
40*833e5d42SEmmanuel Vadot  clocks:
41*833e5d42SEmmanuel Vadot    maxItems: 1
42*833e5d42SEmmanuel Vadot
43*833e5d42SEmmanuel Vadot  '#clock-cells':
44*833e5d42SEmmanuel Vadot    const: 1
45*833e5d42SEmmanuel Vadot
46*833e5d42SEmmanuel Vadot  clock-output-names:
47*833e5d42SEmmanuel Vadot    items:
48*833e5d42SEmmanuel Vadot      - const: cpu
49*833e5d42SEmmanuel Vadot      - const: ddr
50*833e5d42SEmmanuel Vadot      - const: ahb
51*833e5d42SEmmanuel Vadot
52*833e5d42SEmmanuel Vadotrequired:
53*833e5d42SEmmanuel Vadot  - compatible
54*833e5d42SEmmanuel Vadot  - reg
55*833e5d42SEmmanuel Vadot  - clock-names
56*833e5d42SEmmanuel Vadot  - clocks
57*833e5d42SEmmanuel Vadot  - '#clock-cells'
58*833e5d42SEmmanuel Vadot
59*833e5d42SEmmanuel VadotadditionalProperties: false
60*833e5d42SEmmanuel Vadot
61*833e5d42SEmmanuel Vadotexamples:
62*833e5d42SEmmanuel Vadot  - |
63*833e5d42SEmmanuel Vadot    clock-controller@18050000 {
64*833e5d42SEmmanuel Vadot        compatible = "qca,ar9132-pll", "qca,ar9130-pll";
65*833e5d42SEmmanuel Vadot        reg = <0x18050000 0x20>;
66*833e5d42SEmmanuel Vadot        clock-names = "ref";
67*833e5d42SEmmanuel Vadot        clocks = <&extosc>;
68*833e5d42SEmmanuel Vadot        #clock-cells = <1>;
69*833e5d42SEmmanuel Vadot        clock-output-names = "cpu", "ddr", "ahb";
70*833e5d42SEmmanuel Vadot    };
71