1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Microchip PolarFire Clock Control Module Binding 8 9maintainers: 10 - Daire McNamara <daire.mcnamara@microchip.com> 11 12description: | 13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller, 14 which gates and enables all peripheral clocks. 15 16 This device tree binding describes 33 gate clocks. Clocks are referenced by 17 user nodes by the CLKCFG node phandle and the clock index in the group, from 18 0 to 32. 19 20properties: 21 compatible: 22 const: microchip,mpfs-clkcfg 23 24 reg: 25 items: 26 - description: | 27 clock config registers: 28 These registers contain enable, reset & divider tables for the, cpu, 29 axi, ahb and rtc/mtimer reference clocks as well as enable and reset 30 for the peripheral clocks. 31 - description: | 32 mss pll dri registers: 33 Block of registers responsible for dynamic reconfiguration of the mss 34 pll 35 36 clocks: 37 maxItems: 1 38 39 '#clock-cells': 40 const: 1 41 description: | 42 The clock consumer should specify the desired clock by having the clock 43 ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h 44 for the full list of PolarFire clock IDs. 45 46required: 47 - compatible 48 - reg 49 - clocks 50 - '#clock-cells' 51 52additionalProperties: false 53 54examples: 55 # Clock Config node: 56 - | 57 #include <dt-bindings/clock/microchip,mpfs-clock.h> 58 soc { 59 #address-cells = <2>; 60 #size-cells = <2>; 61 clkcfg: clock-controller@20002000 { 62 compatible = "microchip,mpfs-clkcfg"; 63 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; 64 clocks = <&ref>; 65 #clock-cells = <1>; 66 }; 67 }; 68