1*b2d2a78aSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*b2d2a78aSEmmanuel Vadot%YAML 1.2 3*b2d2a78aSEmmanuel Vadot--- 4*b2d2a78aSEmmanuel Vadot$id: http://devicetree.org/schemas/clock/mediatek,infracfg.yaml# 5*b2d2a78aSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*b2d2a78aSEmmanuel Vadot 7*b2d2a78aSEmmanuel Vadottitle: MediaTek Infrastructure System Configuration Controller 8*b2d2a78aSEmmanuel Vadot 9*b2d2a78aSEmmanuel Vadotmaintainers: 10*b2d2a78aSEmmanuel Vadot - Matthias Brugger <matthias.bgg@gmail.com> 11*b2d2a78aSEmmanuel Vadot 12*b2d2a78aSEmmanuel Vadotdescription: 13*b2d2a78aSEmmanuel Vadot The Mediatek infracfg controller provides various clocks and reset outputs 14*b2d2a78aSEmmanuel Vadot to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>, 15*b2d2a78aSEmmanuel Vadot and reset values in <dt-bindings/reset/mt*-reset.h> and 16*b2d2a78aSEmmanuel Vadot <dt-bindings/reset/mt*-resets.h>. 17*b2d2a78aSEmmanuel Vadot 18*b2d2a78aSEmmanuel Vadotproperties: 19*b2d2a78aSEmmanuel Vadot compatible: 20*b2d2a78aSEmmanuel Vadot oneOf: 21*b2d2a78aSEmmanuel Vadot - items: 22*b2d2a78aSEmmanuel Vadot - enum: 23*b2d2a78aSEmmanuel Vadot - mediatek,mt2701-infracfg 24*b2d2a78aSEmmanuel Vadot - mediatek,mt2712-infracfg 25*b2d2a78aSEmmanuel Vadot - mediatek,mt6765-infracfg 26*b2d2a78aSEmmanuel Vadot - mediatek,mt6795-infracfg 27*b2d2a78aSEmmanuel Vadot - mediatek,mt6779-infracfg_ao 28*b2d2a78aSEmmanuel Vadot - mediatek,mt6797-infracfg 29*b2d2a78aSEmmanuel Vadot - mediatek,mt7622-infracfg 30*b2d2a78aSEmmanuel Vadot - mediatek,mt7629-infracfg 31*b2d2a78aSEmmanuel Vadot - mediatek,mt7981-infracfg 32*b2d2a78aSEmmanuel Vadot - mediatek,mt7986-infracfg 33*b2d2a78aSEmmanuel Vadot - mediatek,mt7988-infracfg 34*b2d2a78aSEmmanuel Vadot - mediatek,mt8135-infracfg 35*b2d2a78aSEmmanuel Vadot - mediatek,mt8167-infracfg 36*b2d2a78aSEmmanuel Vadot - mediatek,mt8173-infracfg 37*b2d2a78aSEmmanuel Vadot - mediatek,mt8183-infracfg 38*b2d2a78aSEmmanuel Vadot - mediatek,mt8516-infracfg 39*b2d2a78aSEmmanuel Vadot - const: syscon 40*b2d2a78aSEmmanuel Vadot - items: 41*b2d2a78aSEmmanuel Vadot - const: mediatek,mt7623-infracfg 42*b2d2a78aSEmmanuel Vadot - const: mediatek,mt2701-infracfg 43*b2d2a78aSEmmanuel Vadot - const: syscon 44*b2d2a78aSEmmanuel Vadot 45*b2d2a78aSEmmanuel Vadot reg: 46*b2d2a78aSEmmanuel Vadot maxItems: 1 47*b2d2a78aSEmmanuel Vadot 48*b2d2a78aSEmmanuel Vadot '#clock-cells': 49*b2d2a78aSEmmanuel Vadot const: 1 50*b2d2a78aSEmmanuel Vadot 51*b2d2a78aSEmmanuel Vadot '#reset-cells': 52*b2d2a78aSEmmanuel Vadot const: 1 53*b2d2a78aSEmmanuel Vadot 54*b2d2a78aSEmmanuel Vadotrequired: 55*b2d2a78aSEmmanuel Vadot - compatible 56*b2d2a78aSEmmanuel Vadot - reg 57*b2d2a78aSEmmanuel Vadot - '#clock-cells' 58*b2d2a78aSEmmanuel Vadot 59*b2d2a78aSEmmanuel Vadotif: 60*b2d2a78aSEmmanuel Vadot properties: 61*b2d2a78aSEmmanuel Vadot compatible: 62*b2d2a78aSEmmanuel Vadot contains: 63*b2d2a78aSEmmanuel Vadot enum: 64*b2d2a78aSEmmanuel Vadot - mediatek,mt2701-infracfg 65*b2d2a78aSEmmanuel Vadot - mediatek,mt2712-infracfg 66*b2d2a78aSEmmanuel Vadot - mediatek,mt6795-infracfg 67*b2d2a78aSEmmanuel Vadot - mediatek,mt7622-infracfg 68*b2d2a78aSEmmanuel Vadot - mediatek,mt7986-infracfg 69*b2d2a78aSEmmanuel Vadot - mediatek,mt8135-infracfg 70*b2d2a78aSEmmanuel Vadot - mediatek,mt8173-infracfg 71*b2d2a78aSEmmanuel Vadot - mediatek,mt8183-infracfg 72*b2d2a78aSEmmanuel Vadotthen: 73*b2d2a78aSEmmanuel Vadot required: 74*b2d2a78aSEmmanuel Vadot - '#reset-cells' 75*b2d2a78aSEmmanuel Vadot 76*b2d2a78aSEmmanuel VadotadditionalProperties: false 77*b2d2a78aSEmmanuel Vadot 78*b2d2a78aSEmmanuel Vadotexamples: 79*b2d2a78aSEmmanuel Vadot - | 80*b2d2a78aSEmmanuel Vadot infracfg: clock-controller@10001000 { 81*b2d2a78aSEmmanuel Vadot compatible = "mediatek,mt8173-infracfg", "syscon"; 82*b2d2a78aSEmmanuel Vadot reg = <0x10001000 0x1000>; 83*b2d2a78aSEmmanuel Vadot #clock-cells = <1>; 84*b2d2a78aSEmmanuel Vadot #reset-cells = <1>; 85*b2d2a78aSEmmanuel Vadot }; 86