1Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator 2 3This device exposes 4 clocks in total: 4 5- MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz 6- MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete 7 frequencies 8- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT 9 10MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set 11requests. 12 13Required properties: 14- compatible: "maxim,max9485" 15- clocks: Input clock, must provice 27.000 MHz 16- clock-names: Must be set to "xclk" 17- #clock-cells: From common clock binding; shall be set to 1 18 19Optional properties: 20- reset-gpios: GPIO descriptor connected to the #RESET input pin 21- vdd-supply: A regulator node for Vdd 22- clock-output-names: Name of output clocks, as defined in common clock 23 bindings 24 25If not explicitly set, the output names are "mclkout", "clkout", "clkout1" 26and "clkout2". 27 28Clocks are defined as preprocessor macros in the dt-binding header. 29 30Example: 31 32 #include <dt-bindings/clock/maxim,max9485.h> 33 34 xo-27mhz: xo-27mhz { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <27000000>; 38 }; 39 40 &i2c0 { 41 max9485: audio-clock@63 { 42 reg = <0x63>; 43 compatible = "maxim,max9485"; 44 clock-names = "xclk"; 45 clocks = <&xo-27mhz>; 46 reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; 47 vdd-supply = <&3v3-reg>; 48 #clock-cells = <1>; 49 }; 50 }; 51 52 // Clock consumer node 53 54 foo@0 { 55 compatible = "bar,foo"; 56 /* ... */ 57 clock-names = "foo-input-clk"; 58 clocks = <&max9485 MAX9485_CLKOUT1>; 59 }; 60