xref: /freebsd/sys/contrib/device-tree/Bindings/clock/imx8qxp-lpcg.yaml (revision 6be3386466ab79a84b48429ae66244f21526d3df) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
8
9maintainers:
10  - Aisheng Dong <aisheng.dong@nxp.com>
11
12description: |
13  The Low-Power Clock Gate (LPCG) modules contain a local programming
14  model to control the clock gates for the peripherals. An LPCG module
15  is used to locally gate the clocks for the associated peripheral.
16
17  This level of clock gating is provided after the clocks are generated
18  by the SCU resources and clock controls. Thus even if the clock is
19  enabled by these control bits, it might still not be running based
20  on the base resource.
21
22  The clock consumer should specify the desired clock by having the clock
23  ID in its "clocks" phandle cell. See the full list of clock IDs from:
24  include/dt-bindings/clock/imx8-clock.h
25
26properties:
27  compatible:
28    enum:
29      - fsl,imx8qxp-lpcg-adma
30      - fsl,imx8qxp-lpcg-conn
31      - fsl,imx8qxp-lpcg-dc
32      - fsl,imx8qxp-lpcg-dsp
33      - fsl,imx8qxp-lpcg-gpu
34      - fsl,imx8qxp-lpcg-hsio
35      - fsl,imx8qxp-lpcg-img
36      - fsl,imx8qxp-lpcg-lsio
37      - fsl,imx8qxp-lpcg-vpu
38
39  reg:
40    maxItems: 1
41
42  '#clock-cells':
43    const: 1
44
45required:
46  - compatible
47  - reg
48  - '#clock-cells'
49
50additionalProperties: false
51
52examples:
53  - |
54    #include <dt-bindings/clock/imx8-clock.h>
55    #include <dt-bindings/firmware/imx/rsrc.h>
56    #include <dt-bindings/interrupt-controller/arm-gic.h>
57
58    clock-controller@5b200000 {
59        compatible = "fsl,imx8qxp-lpcg-conn";
60        reg = <0x5b200000 0xb0000>;
61        #clock-cells = <1>;
62    };
63
64    mmc@5b010000 {
65        compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
66        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
67        reg = <0x5b010000 0x10000>;
68        clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
69                 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
70                 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
71        clock-names = "ipg", "per", "ahb";
72        power-domains = <&pd IMX_SC_R_SDHC_0>;
73    };
74