1* Clock bindings for Freescale i.MX7ULP 2 3i.MX7ULP Clock functions are under joint control of the System 4Clock Generation (SCG) modules, Peripheral Clock Control (PCC) 5modules, and Core Mode Controller (CMC)1 blocks 6 7The clocking scheme provides clear separation between M4 domain 8and A7 domain. Except for a few clock sources shared between two 9domains, such as the System Oscillator clock, the Slow IRC (SIRC), 10and and the Fast IRC clock (FIRCLK), clock sources and clock 11management are separated and contained within each domain. 12 13M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. 14A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. 15 16Note: this binding doc is only for A7 clock domain. 17 18System Clock Generation (SCG) modules: 19--------------------------------------------------------------------- 20The System Clock Generation (SCG) is responsible for clock generation 21and distribution across this device. Functions performed by the SCG 22include: clock reference selection, generation of clock used to derive 23processor, system, peripheral bus and external memory interface clocks, 24source selection for peripheral clocks and control of power saving 25clock gating mode. 26 27Required properties: 28 29- compatible: Should be "fsl,imx7ulp-scg1". 30- reg : Should contain registers location and length. 31- #clock-cells: Should be <1>. 32- clocks: Should contain the fixed input clocks. 33- clock-names: Should contain the following clock names: 34 "rosc", "sosc", "sirc", "firc", "upll", "mpll". 35 36Peripheral Clock Control (PCC) modules: 37--------------------------------------------------------------------- 38The Peripheral Clock Control (PCC) is responsible for clock selection, 39optional division and clock gating mode for peripherals in their 40respected power domain 41 42Required properties: 43- compatible: Should be one of: 44 "fsl,imx7ulp-pcc2", 45 "fsl,imx7ulp-pcc3". 46- reg : Should contain registers location and length. 47- #clock-cells: Should be <1>. 48- clocks: Should contain the fixed input clocks. 49- clock-names: Should contain the following clock names: 50 "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", 51 "apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk", 52 "mpll", "firc_bus_clk", "rosc", "spll_bus_clk"; 53 54The clock consumer should specify the desired clock by having the clock 55ID in its "clocks" phandle cell. 56See include/dt-bindings/clock/imx7ulp-clock.h 57for the full list of i.MX7ULP clock IDs of each module. 58 59Examples: 60 61#include <dt-bindings/clock/imx7ulp-clock.h> 62 63scg1: scg1@403e0000 { 64 compatible = "fsl,imx7ulp-scg1; 65 reg = <0x403e0000 0x10000>; 66 clocks = <&rosc>, <&sosc>, <&sirc>, 67 <&firc>, <&upll>, <&mpll>; 68 clock-names = "rosc", "sosc", "sirc", 69 "firc", "upll", "mpll"; 70 #clock-cells = <1>; 71}; 72 73pcc2: pcc2@403f0000 { 74 compatible = "fsl,imx7ulp-pcc2"; 75 reg = <0x403f0000 0x10000>; 76 #clock-cells = <1>; 77 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 78 <&scg1 IMX7ULP_CLK_NIC1_DIV>, 79 <&scg1 IMX7ULP_CLK_DDR_DIV>, 80 <&scg1 IMX7ULP_CLK_APLL_PFD2>, 81 <&scg1 IMX7ULP_CLK_APLL_PFD1>, 82 <&scg1 IMX7ULP_CLK_APLL_PFD0>, 83 <&scg1 IMX7ULP_CLK_UPLL>, 84 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, 85 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, 86 <&scg1 IMX7ULP_CLK_ROSC>, 87 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; 88 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", 89 "apll_pfd2", "apll_pfd1", "apll_pfd0", 90 "upll", "sosc_bus_clk", "mpll", 91 "firc_bus_clk", "rosc", "spll_bus_clk"; 92}; 93 94usdhc1: usdhc@40380000 { 95 compatible = "fsl,imx7ulp-usdhc"; 96 reg = <0x40380000 0x10000>; 97 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 99 <&scg1 IMX7ULP_CLK_NIC1_DIV>, 100 <&pcc2 IMX7ULP_CLK_USDHC1>; 101 clock-names ="ipg", "ahb", "per"; 102 bus-width = <4>; 103}; 104