1* Samsung Exynos5433 CMU (Clock Management Units) 2 3The Exynos5433 clock controller generates and supplies clock to various 4controllers within the Exynos5433 SoC. 5 6Required Properties: 7 8- compatible: should be one of the following. 9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP 10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS 11 domains and bus clocks. 12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF 13 which generates clocks for LLI (Low Latency Interface) IP. 14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF 15 which generates clocks for DRAM Memory Controller domain. 16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC 17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs. 18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS 19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs. 20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS 21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs. 22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D 23 which generates clocks for G2D/MDMA IPs. 24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP 25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs. 26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD 27 which generates clocks for Cortex-A5/BUS/AUDIO clocks. 28 - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1" 29 and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS 30 which generates global data buses clock and global peripheral buses clock. 31 - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D 32 which generates clocks for 3D Graphics Engine IP. 33 - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL 34 which generates clocks for GSCALER IPs. 35 - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO 36 which generates clocks for Cortex-A53 Quad-core processor. 37 - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS 38 which generates clocks for Cortex-A57 Quad-core processor, CoreSight and 39 L2 cache controller. 40 - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL 41 which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs. 42 - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC 43 which generates clocks for MFC(Multi-Format Codec) IP. 44 - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC 45 which generates clocks for HEVC(High Efficiency Video Codec) decoder IP. 46 - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP 47 which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. 48 - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0 49 which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} 50 IPs. 51 - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1 52 which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. 53 - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM 54 which generates clocks for SSS (Security SubSystem) and SlimSSS IPs. 55 56- reg: physical base address of the controller and length of memory mapped 57 region. 58 59- #clock-cells: should be 1. 60 61- clocks: list of the clock controller input clock identifiers, 62 from common clock bindings. Please refer the next section 63 to find the input clocks for a given controller. 64 65- clock-names: list of the clock controller input clock names, 66 as described in clock-bindings.txt. 67 68 Input clocks for top clock controller: 69 - oscclk 70 - sclk_mphy_pll 71 - sclk_mfc_pll 72 - sclk_bus_pll 73 74 Input clocks for cpif clock controller: 75 - oscclk 76 77 Input clocks for mif clock controller: 78 - oscclk 79 - sclk_mphy_pll 80 81 Input clocks for fsys clock controller: 82 - oscclk 83 - sclk_ufs_mphy 84 - aclk_fsys_200 85 - sclk_pcie_100_fsys 86 - sclk_ufsunipro_fsys 87 - sclk_mmc2_fsys 88 - sclk_mmc1_fsys 89 - sclk_mmc0_fsys 90 - sclk_usbhost30_fsys 91 - sclk_usbdrd30_fsys 92 93 Input clocks for g2d clock controller: 94 - oscclk 95 - aclk_g2d_266 96 - aclk_g2d_400 97 98 Input clocks for disp clock controller: 99 - oscclk 100 - sclk_dsim1_disp 101 - sclk_dsim0_disp 102 - sclk_dsd_disp 103 - sclk_decon_tv_eclk_disp 104 - sclk_decon_vclk_disp 105 - sclk_decon_eclk_disp 106 - sclk_decon_tv_vclk_disp 107 - aclk_disp_333 108 109 Input clocks for audio clock controller: 110 - oscclk 111 - fout_aud_pll 112 113 Input clocks for bus0 clock controller: 114 - aclk_bus0_400 115 116 Input clocks for bus1 clock controller: 117 - aclk_bus1_400 118 119 Input clocks for bus2 clock controller: 120 - oscclk 121 - aclk_bus2_400 122 123 Input clocks for g3d clock controller: 124 - oscclk 125 - aclk_g3d_400 126 127 Input clocks for gscl clock controller: 128 - oscclk 129 - aclk_gscl_111 130 - aclk_gscl_333 131 132 Input clocks for apollo clock controller: 133 - oscclk 134 - sclk_bus_pll_apollo 135 136 Input clocks for atlas clock controller: 137 - oscclk 138 - sclk_bus_pll_atlas 139 140 Input clocks for mscl clock controller: 141 - oscclk 142 - sclk_jpeg_mscl 143 - aclk_mscl_400 144 145 Input clocks for mfc clock controller: 146 - oscclk 147 - aclk_mfc_400 148 149 Input clocks for hevc clock controller: 150 - oscclk 151 - aclk_hevc_400 152 153 Input clocks for isp clock controller: 154 - oscclk 155 - aclk_isp_dis_400 156 - aclk_isp_400 157 158 Input clocks for cam0 clock controller: 159 - oscclk 160 - aclk_cam0_333 161 - aclk_cam0_400 162 - aclk_cam0_552 163 164 Input clocks for cam1 clock controller: 165 - oscclk 166 - sclk_isp_uart_cam1 167 - sclk_isp_spi1_cam1 168 - sclk_isp_spi0_cam1 169 - aclk_cam1_333 170 - aclk_cam1_400 171 - aclk_cam1_552 172 173 Input clocks for imem clock controller: 174 - oscclk 175 - aclk_imem_sssx_266 176 - aclk_imem_266 177 - aclk_imem_200 178 179Optional properties: 180 - power-domains: a phandle to respective power domain node as described by 181 generic PM domain bindings (see power/power_domain.txt for more 182 information). 183 184Each clock is assigned an identifier and client nodes can use this identifier 185to specify the clock which they consume. 186 187All available clocks are defined as preprocessor macros in 188dt-bindings/clock/exynos5433.h header and can be used in device 189tree sources. 190 191Example 1: Examples of 'oscclk' source clock node are listed below. 192 193 xxti: xxti { 194 compatible = "fixed-clock"; 195 clock-output-names = "oscclk"; 196 #clock-cells = <0>; 197 }; 198 199Example 2: Examples of clock controller nodes are listed below. 200 201 cmu_top: clock-controller@10030000 { 202 compatible = "samsung,exynos5433-cmu-top"; 203 reg = <0x10030000 0x0c04>; 204 #clock-cells = <1>; 205 206 clock-names = "oscclk", 207 "sclk_mphy_pll", 208 "sclk_mfc_pll", 209 "sclk_bus_pll"; 210 clocks = <&xxti>, 211 <&cmu_cpif CLK_SCLK_MPHY_PLL>, 212 <&cmu_mif CLK_SCLK_MFC_PLL>, 213 <&cmu_mif CLK_SCLK_BUS_PLL>; 214 }; 215 216 cmu_cpif: clock-controller@10fc0000 { 217 compatible = "samsung,exynos5433-cmu-cpif"; 218 reg = <0x10fc0000 0x0c04>; 219 #clock-cells = <1>; 220 221 clock-names = "oscclk"; 222 clocks = <&xxti>; 223 }; 224 225 cmu_mif: clock-controller@105b0000 { 226 compatible = "samsung,exynos5433-cmu-mif"; 227 reg = <0x105b0000 0x100c>; 228 #clock-cells = <1>; 229 230 clock-names = "oscclk", 231 "sclk_mphy_pll"; 232 clocks = <&xxti>, 233 <&cmu_cpif CLK_SCLK_MPHY_PLL>; 234 }; 235 236 cmu_peric: clock-controller@14c80000 { 237 compatible = "samsung,exynos5433-cmu-peric"; 238 reg = <0x14c80000 0x0b08>; 239 #clock-cells = <1>; 240 }; 241 242 cmu_peris: clock-controller@10040000 { 243 compatible = "samsung,exynos5433-cmu-peris"; 244 reg = <0x10040000 0x0b20>; 245 #clock-cells = <1>; 246 }; 247 248 cmu_fsys: clock-controller@156e0000 { 249 compatible = "samsung,exynos5433-cmu-fsys"; 250 reg = <0x156e0000 0x0b04>; 251 #clock-cells = <1>; 252 253 clock-names = "oscclk", 254 "sclk_ufs_mphy", 255 "aclk_fsys_200", 256 "sclk_pcie_100_fsys", 257 "sclk_ufsunipro_fsys", 258 "sclk_mmc2_fsys", 259 "sclk_mmc1_fsys", 260 "sclk_mmc0_fsys", 261 "sclk_usbhost30_fsys", 262 "sclk_usbdrd30_fsys"; 263 clocks = <&xxti>, 264 <&cmu_cpif CLK_SCLK_UFS_MPHY>, 265 <&cmu_top CLK_ACLK_FSYS_200>, 266 <&cmu_top CLK_SCLK_PCIE_100_FSYS>, 267 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, 268 <&cmu_top CLK_SCLK_MMC2_FSYS>, 269 <&cmu_top CLK_SCLK_MMC1_FSYS>, 270 <&cmu_top CLK_SCLK_MMC0_FSYS>, 271 <&cmu_top CLK_SCLK_USBHOST30_FSYS>, 272 <&cmu_top CLK_SCLK_USBDRD30_FSYS>; 273 }; 274 275 cmu_g2d: clock-controller@12460000 { 276 compatible = "samsung,exynos5433-cmu-g2d"; 277 reg = <0x12460000 0x0b08>; 278 #clock-cells = <1>; 279 280 clock-names = "oscclk", 281 "aclk_g2d_266", 282 "aclk_g2d_400"; 283 clocks = <&xxti>, 284 <&cmu_top CLK_ACLK_G2D_266>, 285 <&cmu_top CLK_ACLK_G2D_400>; 286 power-domains = <&pd_g2d>; 287 }; 288 289 cmu_disp: clock-controller@13b90000 { 290 compatible = "samsung,exynos5433-cmu-disp"; 291 reg = <0x13b90000 0x0c04>; 292 #clock-cells = <1>; 293 294 clock-names = "oscclk", 295 "sclk_dsim1_disp", 296 "sclk_dsim0_disp", 297 "sclk_dsd_disp", 298 "sclk_decon_tv_eclk_disp", 299 "sclk_decon_vclk_disp", 300 "sclk_decon_eclk_disp", 301 "sclk_decon_tv_vclk_disp", 302 "aclk_disp_333"; 303 clocks = <&xxti>, 304 <&cmu_mif CLK_SCLK_DSIM1_DISP>, 305 <&cmu_mif CLK_SCLK_DSIM0_DISP>, 306 <&cmu_mif CLK_SCLK_DSD_DISP>, 307 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, 308 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, 309 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, 310 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, 311 <&cmu_mif CLK_ACLK_DISP_333>; 312 power-domains = <&pd_disp>; 313 }; 314 315 cmu_aud: clock-controller@114c0000 { 316 compatible = "samsung,exynos5433-cmu-aud"; 317 reg = <0x114c0000 0x0b04>; 318 #clock-cells = <1>; 319 320 clock-names = "oscclk", "fout_aud_pll"; 321 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; 322 power-domains = <&pd_aud>; 323 }; 324 325 cmu_bus0: clock-controller@13600000 { 326 compatible = "samsung,exynos5433-cmu-bus0"; 327 reg = <0x13600000 0x0b04>; 328 #clock-cells = <1>; 329 330 clock-names = "aclk_bus0_400"; 331 clocks = <&cmu_top CLK_ACLK_BUS0_400>; 332 }; 333 334 cmu_bus1: clock-controller@14800000 { 335 compatible = "samsung,exynos5433-cmu-bus1"; 336 reg = <0x14800000 0x0b04>; 337 #clock-cells = <1>; 338 339 clock-names = "aclk_bus1_400"; 340 clocks = <&cmu_top CLK_ACLK_BUS1_400>; 341 }; 342 343 cmu_bus2: clock-controller@13400000 { 344 compatible = "samsung,exynos5433-cmu-bus2"; 345 reg = <0x13400000 0x0b04>; 346 #clock-cells = <1>; 347 348 clock-names = "oscclk", "aclk_bus2_400"; 349 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; 350 }; 351 352 cmu_g3d: clock-controller@14aa0000 { 353 compatible = "samsung,exynos5433-cmu-g3d"; 354 reg = <0x14aa0000 0x1000>; 355 #clock-cells = <1>; 356 357 clock-names = "oscclk", "aclk_g3d_400"; 358 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; 359 power-domains = <&pd_g3d>; 360 }; 361 362 cmu_gscl: clock-controller@13cf0000 { 363 compatible = "samsung,exynos5433-cmu-gscl"; 364 reg = <0x13cf0000 0x0b10>; 365 #clock-cells = <1>; 366 367 clock-names = "oscclk", 368 "aclk_gscl_111", 369 "aclk_gscl_333"; 370 clocks = <&xxti>, 371 <&cmu_top CLK_ACLK_GSCL_111>, 372 <&cmu_top CLK_ACLK_GSCL_333>; 373 power-domains = <&pd_gscl>; 374 }; 375 376 cmu_apollo: clock-controller@11900000 { 377 compatible = "samsung,exynos5433-cmu-apollo"; 378 reg = <0x11900000 0x1088>; 379 #clock-cells = <1>; 380 381 clock-names = "oscclk", "sclk_bus_pll_apollo"; 382 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; 383 }; 384 385 cmu_atlas: clock-controller@11800000 { 386 compatible = "samsung,exynos5433-cmu-atlas"; 387 reg = <0x11800000 0x1088>; 388 #clock-cells = <1>; 389 390 clock-names = "oscclk", "sclk_bus_pll_atlas"; 391 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; 392 }; 393 394 cmu_mscl: clock-controller@105d0000 { 395 compatible = "samsung,exynos5433-cmu-mscl"; 396 reg = <0x105d0000 0x0b10>; 397 #clock-cells = <1>; 398 399 clock-names = "oscclk", 400 "sclk_jpeg_mscl", 401 "aclk_mscl_400"; 402 clocks = <&xxti>, 403 <&cmu_top CLK_SCLK_JPEG_MSCL>, 404 <&cmu_top CLK_ACLK_MSCL_400>; 405 power-domains = <&pd_mscl>; 406 }; 407 408 cmu_mfc: clock-controller@15280000 { 409 compatible = "samsung,exynos5433-cmu-mfc"; 410 reg = <0x15280000 0x0b08>; 411 #clock-cells = <1>; 412 413 clock-names = "oscclk", "aclk_mfc_400"; 414 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; 415 power-domains = <&pd_mfc>; 416 }; 417 418 cmu_hevc: clock-controller@14f80000 { 419 compatible = "samsung,exynos5433-cmu-hevc"; 420 reg = <0x14f80000 0x0b08>; 421 #clock-cells = <1>; 422 423 clock-names = "oscclk", "aclk_hevc_400"; 424 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; 425 power-domains = <&pd_hevc>; 426 }; 427 428 cmu_isp: clock-controller@146d0000 { 429 compatible = "samsung,exynos5433-cmu-isp"; 430 reg = <0x146d0000 0x0b0c>; 431 #clock-cells = <1>; 432 433 clock-names = "oscclk", 434 "aclk_isp_dis_400", 435 "aclk_isp_400"; 436 clocks = <&xxti>, 437 <&cmu_top CLK_ACLK_ISP_DIS_400>, 438 <&cmu_top CLK_ACLK_ISP_400>; 439 power-domains = <&pd_isp>; 440 }; 441 442 cmu_cam0: clock-controller@120d0000 { 443 compatible = "samsung,exynos5433-cmu-cam0"; 444 reg = <0x120d0000 0x0b0c>; 445 #clock-cells = <1>; 446 447 clock-names = "oscclk", 448 "aclk_cam0_333", 449 "aclk_cam0_400", 450 "aclk_cam0_552"; 451 clocks = <&xxti>, 452 <&cmu_top CLK_ACLK_CAM0_333>, 453 <&cmu_top CLK_ACLK_CAM0_400>, 454 <&cmu_top CLK_ACLK_CAM0_552>; 455 power-domains = <&pd_cam0>; 456 }; 457 458 cmu_cam1: clock-controller@145d0000 { 459 compatible = "samsung,exynos5433-cmu-cam1"; 460 reg = <0x145d0000 0x0b08>; 461 #clock-cells = <1>; 462 463 clock-names = "oscclk", 464 "sclk_isp_uart_cam1", 465 "sclk_isp_spi1_cam1", 466 "sclk_isp_spi0_cam1", 467 "aclk_cam1_333", 468 "aclk_cam1_400", 469 "aclk_cam1_552"; 470 clocks = <&xxti>, 471 <&cmu_top CLK_SCLK_ISP_UART_CAM1>, 472 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, 473 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, 474 <&cmu_top CLK_ACLK_CAM1_333>, 475 <&cmu_top CLK_ACLK_CAM1_400>, 476 <&cmu_top CLK_ACLK_CAM1_552>; 477 power-domains = <&pd_cam1>; 478 }; 479 480 cmu_imem: clock-controller@11060000 { 481 compatible = "samsung,exynos5433-cmu-imem"; 482 reg = <0x11060000 0x1000>; 483 #clock-cells = <1>; 484 485 clock-names = "oscclk", 486 "aclk_imem_sssx_266", 487 "aclk_imem_266", 488 "aclk_imem_200"; 489 clocks = <&xxti>, 490 <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, 491 <&cmu_top CLK_DIV_ACLK_IMEM_266>, 492 <&cmu_top CLK_DIV_ACLK_IMEM_200>; 493 }; 494 495Example 3: UART controller node that consumes the clock generated by the clock 496 controller. 497 498 serial_0: serial@14c10000 { 499 compatible = "samsung,exynos5433-uart"; 500 reg = <0x14C10000 0x100>; 501 interrupts = <0 421 0>; 502 clocks = <&cmu_peric CLK_PCLK_UART0>, 503 <&cmu_peric CLK_SCLK_UART0>; 504 clock-names = "uart", "clk_uart_baud0"; 505 pinctrl-names = "default"; 506 pinctrl-0 = <&uart0_bus>; 507 }; 508