1PLL divider based Dove clocks 2 3Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide 4high speed clocks for a number of peripherals. These dividers are part of 5the PMU, and thus this node should be a child of the PMU node. 6 7The following clocks are provided: 8 9ID Clock 10------------- 110 AXI bus clock 121 GPU clock 132 VMeta clock 143 LCD clock 15 16Required properties: 17- compatible : shall be "marvell,dove-divider-clock" 18- reg : shall be the register address of the Core PLL and Clock Divider 19 Control 0 register. This will cover that register, as well as the 20 Core PLL and Clock Divider Control 1 register. Thus, it will have 21 a size of 8. 22- #clock-cells : from common clock binding; shall be set to 1 23 24divider_clk: core-clock@64 { 25 compatible = "marvell,dove-divider-clock"; 26 reg = <0x0064 0x8>; 27 #clock-cells = <1>; 28}; 29