1* Amlogic AXG Audio Clock Controllers 2 3The Amlogic AXG audio clock controller generates and supplies clock to the 4other elements of the audio subsystem, such as fifos, i2s, spdif and pdm 5devices. 6 7Required Properties: 8 9- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D, 10 "amlogic,g12a-audio-clkc" for G12A, 11 "amlogic,sm1-audio-clkc" for S905X3. 12- reg : physical base address of the clock controller and length of 13 memory mapped region. 14- clocks : a list of phandle + clock-specifier pairs for the clocks listed 15 in clock-names. 16- clock-names : must contain the following: 17 * "pclk" - Main peripheral bus clock 18 may contain the following: 19 * "mst_in[0-7]" - 8 input plls to generate clock signals 20 * "slv_sclk[0-9]" - 10 slave bit clocks provided by external 21 components. 22 * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external 23 components. 24- resets : phandle of the internal reset line 25- #clock-cells : should be 1. 26- #reset-cells : should be 1 on the g12a (and following) soc family 27 28Each clock is assigned an identifier and client nodes can use this identifier 29to specify the clock which they consume. All available clocks are defined as 30preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be 31used in device tree sources. 32 33Example: 34 35clkc_audio: clock-controller@0 { 36 compatible = "amlogic,axg-audio-clkc"; 37 reg = <0x0 0x0 0x0 0xb4>; 38 #clock-cells = <1>; 39 40 clocks = <&clkc CLKID_AUDIO>, 41 <&clkc CLKID_MPLL0>, 42 <&clkc CLKID_MPLL1>, 43 <&clkc CLKID_MPLL2>, 44 <&clkc CLKID_MPLL3>, 45 <&clkc CLKID_HIFI_PLL>, 46 <&clkc CLKID_FCLK_DIV3>, 47 <&clkc CLKID_FCLK_DIV4>, 48 <&clkc CLKID_GP0_PLL>; 49 clock-names = "pclk", 50 "mst_in0", 51 "mst_in1", 52 "mst_in2", 53 "mst_in3", 54 "mst_in4", 55 "mst_in5", 56 "mst_in6", 57 "mst_in7"; 58 resets = <&reset RESET_AUDIO>; 59}; 60