1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Amlogic A1 Peripherals Clock Control Unit 8 9maintainers: 10 - Neil Armstrong <neil.armstrong@linaro.org> 11 - Jerome Brunet <jbrunet@baylibre.com> 12 - Jian Hu <jian.hu@jian.hu.com> 13 - Dmitry Rokosov <ddrokosov@sberdevices.ru> 14 15properties: 16 compatible: 17 const: amlogic,a1-peripherals-clkc 18 19 '#clock-cells': 20 const: 1 21 22 reg: 23 maxItems: 1 24 25 clocks: 26 items: 27 - description: input fixed pll div2 28 - description: input fixed pll div3 29 - description: input fixed pll div5 30 - description: input fixed pll div7 31 - description: input hifi pll 32 - description: input oscillator (usually at 24MHz) 33 34 clock-names: 35 items: 36 - const: fclk_div2 37 - const: fclk_div3 38 - const: fclk_div5 39 - const: fclk_div7 40 - const: hifi_pll 41 - const: xtal 42 43required: 44 - compatible 45 - '#clock-cells' 46 - reg 47 - clocks 48 - clock-names 49 50additionalProperties: false 51 52examples: 53 - | 54 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h> 55 apb { 56 #address-cells = <2>; 57 #size-cells = <2>; 58 59 clock-controller@800 { 60 compatible = "amlogic,a1-peripherals-clkc"; 61 reg = <0 0x800 0 0x104>; 62 #clock-cells = <1>; 63 clocks = <&clkc_pll CLKID_FCLK_DIV2>, 64 <&clkc_pll CLKID_FCLK_DIV3>, 65 <&clkc_pll CLKID_FCLK_DIV5>, 66 <&clkc_pll CLKID_FCLK_DIV7>, 67 <&clkc_pll CLKID_HIFI_PLL>, 68 <&xtal>; 69 clock-names = "fclk_div2", "fclk_div3", 70 "fclk_div5", "fclk_div7", 71 "hifi_pll", "xtal"; 72 }; 73 }; 74