1Broadcom GISB bus Arbiter controller 2 3Required properties: 4 5- compatible: 6 "brcm,bcm7278-gisb-arb" for V7 28nm chips 7 "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips 8 "brcm,bcm7435-gisb-arb" for newer 40nm chips 9 "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips 10 "brcm,bcm7038-gisb-arb" for 130nm chips 11- reg: specifies the base physical address and size of the registers 12- interrupts: specifies the two interrupts (timeout and TEA) to be used from 13 the parent interrupt controller 14 15Optional properties: 16 17- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB 18 masters are valid at the system level 19- brcm,gisb-arb-master-names: string list of the litteral name of the GISB 20 masters. Should match the number of bits set in brcm,gisb-master-mask and 21 the order in which they appear 22 23Example: 24 25gisb-arb@f0400000 { 26 compatible = "brcm,gisb-arb"; 27 reg = <0xf0400000 0x800>; 28 interrupts = <0>, <2>; 29 interrupt-parent = <&sun_l2_intc>; 30 31 brcm,gisb-arb-master-mask = <0x7>; 32 brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; 33}; 34