xref: /freebsd/sys/contrib/device-tree/Bindings/ata/snps,dwc-ahci-common.yaml (revision 59c8e88e72633afbc47a4ace0d2170d00d51f7dc) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DWC AHCI SATA controller properties
8
9maintainers:
10  - Serge Semin <fancer.lancer@gmail.com>
11
12description:
13  This document defines device tree schema for the generic Synopsys DWC
14  AHCI controller properties.
15
16select: false
17
18allOf:
19  - $ref: ahci-common.yaml#
20
21properties:
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  clocks:
29    description:
30      Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
31      PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
32      clock, etc.
33    minItems: 1
34    maxItems: 4
35
36  clock-names:
37    minItems: 1
38    maxItems: 4
39    items:
40      oneOf:
41        - description: Application APB/AHB/AXI BIU clock
42          enum:
43            - pclk
44            - aclk
45            - hclk
46            - sata
47        - description: Power Module keep-alive clock
48          const: pmalive
49        - description: RxOOB detection clock
50          const: rxoob
51        - description: SATA Ports reference clock
52          const: ref
53
54  resets:
55    description:
56      At least basic application and reference clock domains resets are
57      normally supported by the DWC AHCI SATA controller.
58    minItems: 1
59    maxItems: 4
60
61  reset-names:
62    minItems: 1
63    maxItems: 4
64    items:
65      oneOf:
66        - description: Application AHB/AXI BIU clock domain reset control
67          enum:
68            - arst
69            - hrst
70        - description: Power Module keep-alive clock domain reset control
71          const: pmalive
72        - description: RxOOB detection clock domain reset control
73          const: rxoob
74        - description: Reference clock domain reset control
75          const: ref
76
77patternProperties:
78  "^sata-port@[0-9a-e]$":
79    $ref: '#/$defs/dwc-ahci-port'
80
81additionalProperties: true
82
83$defs:
84  dwc-ahci-port:
85    $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
86
87    properties:
88      reg:
89        minimum: 0
90        maximum: 7
91
92      snps,tx-ts-max:
93        $ref: /schemas/types.yaml#/definitions/uint32
94        description: Maximal size of Tx DMA transactions in FIFO words
95        enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
96
97      snps,rx-ts-max:
98        $ref: /schemas/types.yaml#/definitions/uint32
99        description: Maximal size of Rx DMA transactions in FIFO words
100        enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
101
102...
103