1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Tegra Power Management Controller (PMC) 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jonathan Hunter <jonathanh@nvidia.com> 12 13properties: 14 compatible: 15 enum: 16 - nvidia,tegra20-pmc 17 - nvidia,tegra30-pmc 18 - nvidia,tegra114-pmc 19 - nvidia,tegra124-pmc 20 - nvidia,tegra210-pmc 21 22 reg: 23 maxItems: 1 24 description: 25 Offset and length of the register set for the device. 26 27 clock-names: 28 items: 29 - const: pclk 30 - const: clk32k_in 31 description: 32 Must includes entries pclk and clk32k_in. 33 pclk is the Tegra clock of that name and clk32k_in is 32KHz clock 34 input to Tegra. 35 36 clocks: 37 maxItems: 2 38 description: 39 Must contain an entry for each entry in clock-names. 40 See ../clocks/clocks-bindings.txt for details. 41 42 '#clock-cells': 43 const: 1 44 description: 45 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. 46 PMC also has blink control which allows 32Khz clock output to 47 Tegra blink pad. 48 Consumer of PMC clock should specify the desired clock by having 49 the clock ID in its "clocks" phandle cell with pmc clock provider. 50 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC 51 clock IDs. 52 53 '#interrupt-cells': 54 const: 2 55 description: 56 Specifies number of cells needed to encode an interrupt source. 57 The value must be 2. 58 59 interrupt-controller: true 60 61 nvidia,invert-interrupt: 62 $ref: /schemas/types.yaml#/definitions/flag 63 description: Inverts the PMU interrupt signal. 64 The PMU is an external Power Management Unit, whose interrupt output 65 signal is fed into the PMC. This signal is optionally inverted, and 66 then fed into the ARM GIC. The PMC is not involved in the detection 67 or handling of this interrupt signal, merely its inversion. 68 69 nvidia,core-power-req-active-high: 70 $ref: /schemas/types.yaml#/definitions/flag 71 description: Core power request active-high. 72 73 nvidia,sys-clock-req-active-high: 74 $ref: /schemas/types.yaml#/definitions/flag 75 description: System clock request active-high. 76 77 nvidia,combined-power-req: 78 $ref: /schemas/types.yaml#/definitions/flag 79 description: combined power request for CPU and Core. 80 81 nvidia,cpu-pwr-good-en: 82 $ref: /schemas/types.yaml#/definitions/flag 83 description: 84 CPU power good signal from external PMIC to PMC is enabled. 85 86 nvidia,suspend-mode: 87 $ref: /schemas/types.yaml#/definitions/uint32 88 enum: [0, 1, 2] 89 description: 90 The suspend mode that the platform should use. 91 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh 92 Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh 93 Mode 2 is for LP2, CPU voltage off 94 95 nvidia,cpu-pwr-good-time: 96 $ref: /schemas/types.yaml#/definitions/uint32 97 description: CPU power good time in uSec. 98 99 nvidia,cpu-pwr-off-time: 100 $ref: /schemas/types.yaml#/definitions/uint32 101 description: CPU power off time in uSec. 102 103 nvidia,core-pwr-good-time: 104 $ref: /schemas/types.yaml#/definitions/uint32-array 105 description: 106 <Oscillator-stable-time Power-stable-time> 107 Core power good time in uSec. 108 109 nvidia,core-pwr-off-time: 110 $ref: /schemas/types.yaml#/definitions/uint32 111 description: Core power off time in uSec. 112 113 nvidia,lp0-vec: 114 $ref: /schemas/types.yaml#/definitions/uint32-array 115 description: 116 <start length> Starting address and length of LP0 vector. 117 The LP0 vector contains the warm boot code that is executed 118 by AVP when resuming from the LP0 state. 119 The AVP (Audio-Video Processor) is an ARM7 processor and 120 always being the first boot processor when chip is power on 121 or resume from deep sleep mode. When the system is resumed 122 from the deep sleep mode, the warm boot code will restore 123 some PLLs, clocks and then brings up CPU0 for resuming the 124 system. 125 126 core-supply: 127 description: 128 Phandle to voltage regulator connected to the SoC Core power rail. 129 130 core-domain: 131 type: object 132 description: | 133 The vast majority of hardware blocks of Tegra SoC belong to a 134 Core power domain, which has a dedicated voltage rail that powers 135 the blocks. 136 137 properties: 138 operating-points-v2: 139 description: 140 Should contain level, voltages and opp-supported-hw property. 141 The supported-hw is a bitfield indicating SoC speedo or process 142 ID mask. 143 144 "#power-domain-cells": 145 const: 0 146 147 required: 148 - operating-points-v2 149 - "#power-domain-cells" 150 151 additionalProperties: false 152 153 i2c-thermtrip: 154 type: object 155 description: 156 On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, 157 hardware-triggered thermal reset will be enabled. 158 159 properties: 160 nvidia,i2c-controller-id: 161 $ref: /schemas/types.yaml#/definitions/uint32 162 description: 163 ID of I2C controller to send poweroff command to PMU. 164 Valid values are described in section 9.2.148 165 "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference 166 Manual. 167 168 nvidia,bus-addr: 169 $ref: /schemas/types.yaml#/definitions/uint32 170 description: Bus address of the PMU on the I2C bus. 171 172 nvidia,reg-addr: 173 $ref: /schemas/types.yaml#/definitions/uint32 174 description: PMU I2C register address to issue poweroff command. 175 176 nvidia,reg-data: 177 $ref: /schemas/types.yaml#/definitions/uint32 178 description: Poweroff command to write to PMU. 179 180 nvidia,pinmux-id: 181 $ref: /schemas/types.yaml#/definitions/uint32 182 description: 183 Pinmux used by the hardware when issuing Poweroff command. 184 Defaults to 0. Valid values are described in section 12.5.2 185 "Pinmux Support" of the Tegra4 Technical Reference Manual. 186 187 required: 188 - nvidia,i2c-controller-id 189 - nvidia,bus-addr 190 - nvidia,reg-addr 191 - nvidia,reg-data 192 193 additionalProperties: false 194 195 powergates: 196 type: object 197 description: | 198 This node contains a hierarchy of power domain nodes, which should 199 match the powergates on the Tegra SoC. Each powergate node 200 represents a power-domain on the Tegra SoC that can be power-gated 201 by the Tegra PMC. 202 Hardware blocks belonging to a power domain should contain 203 "power-domains" property that is a phandle pointing to corresponding 204 powergate node. 205 The name of the powergate node should be one of the below. Note that 206 not every powergate is applicable to all Tegra devices and the following 207 list shows which powergates are applicable to which devices. 208 Please refer to Tegra TRM for mode details on the powergate nodes to 209 use for each power-gate block inside Tegra. 210 Name Description Devices Applicable 211 3d 3D Graphics Tegra20/114/124/210 212 3d0 3D Graphics 0 Tegra30 213 3d1 3D Graphics 1 Tegra30 214 aud Audio Tegra210 215 dfd Debug Tegra210 216 dis Display A Tegra114/124/210 217 disb Display B Tegra114/124/210 218 heg 2D Graphics Tegra30/114/124/210 219 iram Internal RAM Tegra124/210 220 mpe MPEG Encode All 221 nvdec NVIDIA Video Decode Engine Tegra210 222 nvjpg NVIDIA JPEG Engine Tegra210 223 pcie PCIE Tegra20/30/124/210 224 sata SATA Tegra30/124/210 225 sor Display interfaces Tegra124/210 226 ve2 Video Encode Engine 2 Tegra210 227 venc Video Encode Engine All 228 vdec Video Decode Engine Tegra20/30/114/124 229 vic Video Imaging Compositor Tegra124/210 230 xusba USB Partition A Tegra114/124/210 231 xusbb USB Partition B Tegra114/124/210 232 xusbc USB Partition C Tegra114/124/210 233 234 patternProperties: 235 "^[a-z0-9]+$": 236 type: object 237 additionalProperties: false 238 239 properties: 240 clocks: 241 minItems: 1 242 maxItems: 8 243 description: 244 Must contain an entry for each clock required by the PMC 245 for controlling a power-gate. 246 See ../clocks/clock-bindings.txt document for more details. 247 248 resets: 249 minItems: 1 250 maxItems: 8 251 description: 252 Must contain an entry for each reset required by the PMC 253 for controlling a power-gate. 254 See ../reset/reset.txt for more details. 255 256 power-domains: 257 maxItems: 1 258 259 '#power-domain-cells': 260 const: 0 261 description: Must be 0. 262 263 required: 264 - clocks 265 - resets 266 - '#power-domain-cells' 267 268 additionalProperties: false 269 270patternProperties: 271 "^[a-f0-9]+-[a-f0-9]+$": 272 type: object 273 description: 274 This is a Pad configuration node. On Tegra SOCs a pad is a set of 275 pins which are configured as a group. The pin grouping is a fixed 276 attribute of the hardware. The PMC can be used to set pad power state 277 and signaling voltage. A pad can be either in active or power down mode. 278 The support for power state and signaling voltage configuration varies 279 depending on the pad in question. 3.3V and 1.8V signaling voltages 280 are supported on pins where software controllable signaling voltage 281 switching is available. 282 283 The pad configuration state nodes are placed under the pmc node and they 284 are referred to by the pinctrl client properties. For more information 285 see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. 286 The pad name should be used as the value of the pins property in pin 287 configuration nodes. 288 289 The following pads are present on Tegra124 and Tegra132 290 audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, 291 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, 292 sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. 293 294 The following pads are present on Tegra210 295 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, 296 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, 297 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, 298 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. 299 300 properties: 301 pins: 302 $ref: /schemas/types.yaml#/definitions/string 303 description: Must contain name of the pad(s) to be configured. 304 305 low-power-enable: 306 $ref: /schemas/types.yaml#/definitions/flag 307 description: Configure the pad into power down mode. 308 309 low-power-disable: 310 $ref: /schemas/types.yaml#/definitions/flag 311 description: Configure the pad into active mode. 312 313 power-source: 314 $ref: /schemas/types.yaml#/definitions/uint32 315 description: 316 Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or 317 TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. 318 The values are defined in 319 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. 320 Power state can be configured on all Tegra124 and Tegra132 321 pads. None of the Tegra124 or Tegra132 pads support signaling 322 voltage switching. 323 All of the listed Tegra210 pads except pex-cntrl support power 324 state configuration. Signaling voltage switching is supported 325 on below Tegra210 pads. 326 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, 327 sdmmc3, spi, spi-hv, and uart. 328 329 required: 330 - pins 331 332 additionalProperties: false 333 334required: 335 - compatible 336 - reg 337 - clock-names 338 - clocks 339 - '#clock-cells' 340 341additionalProperties: false 342 343dependencies: 344 "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] 345 "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"] 346 "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"] 347 348examples: 349 - | 350 351 #include <dt-bindings/clock/tegra210-car.h> 352 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 353 #include <dt-bindings/soc/tegra-pmc.h> 354 355 tegra_pmc: pmc@7000e400 { 356 compatible = "nvidia,tegra210-pmc"; 357 reg = <0x7000e400 0x400>; 358 core-supply = <®ulator>; 359 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 360 clock-names = "pclk", "clk32k_in"; 361 #clock-cells = <1>; 362 363 nvidia,invert-interrupt; 364 nvidia,suspend-mode = <0>; 365 nvidia,cpu-pwr-good-time = <0>; 366 nvidia,cpu-pwr-off-time = <0>; 367 nvidia,core-pwr-good-time = <4587 3876>; 368 nvidia,core-pwr-off-time = <39065>; 369 nvidia,core-power-req-active-high; 370 nvidia,sys-clock-req-active-high; 371 372 pd_core: core-domain { 373 operating-points-v2 = <&core_opp_table>; 374 #power-domain-cells = <0>; 375 }; 376 377 powergates { 378 pd_audio: aud { 379 clocks = <&tegra_car TEGRA210_CLK_APE>, 380 <&tegra_car TEGRA210_CLK_APB2APE>; 381 resets = <&tegra_car 198>; 382 power-domains = <&pd_core>; 383 #power-domain-cells = <0>; 384 }; 385 386 pd_xusbss: xusba { 387 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 388 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 389 power-domains = <&pd_core>; 390 #power-domain-cells = <0>; 391 }; 392 }; 393 }; 394