1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: NVIDIA Tegra194 CBB 1.0 8 9maintainers: 10 - Sumit Gupta <sumitg@nvidia.com> 11 12description: |+ 13 The Control Backbone (CBB) is comprised of the physical path from an 14 initiator to a target's register configuration space. CBB 1.0 has 15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various 16 initiators and targets using different bridges like AXIP2P, AXI2APB. 17 18 This driver handles errors due to illegal register accesses reported 19 by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs 20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC" 21 which is the main NOC. 22 23 By default, the access issuing initiator is informed about the error 24 using SError or Data Abort exception unless the ERD (Error Response 25 Disable) is enabled/set for that initiator. If the ERD is enabled, then 26 SError or Data Abort is masked and the error is reported with interrupt. 27 28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the 29 errors due to illegal accesses from CCPLEX are reported by interrupts. 30 If ERD is not set, then error is reported by SError. 31 - For other initiators, the ERD is disabled. So, the access issuing 32 initiator is informed about the illegal access by Data Abort exception. 33 In addition, an interrupt is also generated to CCPLEX. These initiators 34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and 35 engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder 36 engine) etc which can initiate transactions. 37 38 The driver prints relevant debug information like Error Code, Error 39 Description, Master, Address, AXI ID, Cache, Protection, Security Group 40 etc on receiving error notification. 41 42properties: 43 $nodename: 44 pattern: "^[a-z]+-noc@[0-9a-f]+$" 45 46 compatible: 47 enum: 48 - nvidia,tegra194-cbb-noc 49 - nvidia,tegra194-aon-noc 50 - nvidia,tegra194-bpmp-noc 51 - nvidia,tegra194-rce-noc 52 - nvidia,tegra194-sce-noc 53 54 reg: 55 maxItems: 1 56 57 interrupts: 58 description: 59 CCPLEX receives secure or nonsecure interrupt depending on error type. 60 A secure interrupt is received for SEC(firewall) & SLV errors and a 61 non-secure interrupt is received for TMO & DEC errors. 62 items: 63 - description: non-secure interrupt 64 - description: secure interrupt 65 66 nvidia,axi2apb: 67 $ref: '/schemas/types.yaml#/definitions/phandle' 68 description: 69 Specifies the node having all axi2apb bridges which need to be checked 70 for any error logged in their status register. 71 72 nvidia,apbmisc: 73 $ref: '/schemas/types.yaml#/definitions/phandle' 74 description: 75 Specifies the apbmisc node which need to be used for reading the ERD 76 register. 77 78additionalProperties: false 79 80required: 81 - compatible 82 - reg 83 - interrupts 84 - nvidia,apbmisc 85 86examples: 87 - | 88 #include <dt-bindings/interrupt-controller/arm-gic.h> 89 90 cbb-noc@2300000 { 91 compatible = "nvidia,tegra194-cbb-noc"; 92 reg = <0x02300000 0x1000>; 93 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 95 nvidia,axi2apb = <&axi2apb>; 96 nvidia,apbmisc = <&apbmisc>; 97 }; 98