1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner Memory Bus (MBUS) controller 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13description: | 14 The MBUS controller drives the MBUS that other devices in the SoC 15 will use to perform DMA. It also has a register interface that 16 allows to monitor and control the bandwidth and priorities for 17 masters on that bus. 18 19 Each device having to perform their DMA through the MBUS must have 20 the interconnects and interconnect-names properties set to the MBUS 21 controller and with "dma-mem" as the interconnect name. 22 23properties: 24 "#interconnect-cells": 25 const: 1 26 description: 27 The content of the cell is the MBUS ID. 28 29 compatible: 30 enum: 31 - allwinner,sun5i-a13-mbus 32 - allwinner,sun8i-h3-mbus 33 - allwinner,sun50i-a64-mbus 34 35 reg: 36 maxItems: 1 37 38 clocks: 39 maxItems: 1 40 41 dma-ranges: 42 description: 43 See section 2.3.9 of the DeviceTree Specification. 44 45 '#address-cells': true 46 47 '#size-cells': true 48 49required: 50 - "#interconnect-cells" 51 - compatible 52 - reg 53 - clocks 54 - dma-ranges 55 56additionalProperties: false 57 58examples: 59 - | 60 #include <dt-bindings/clock/sun5i-ccu.h> 61 62 mbus: dram-controller@1c01000 { 63 compatible = "allwinner,sun5i-a13-mbus"; 64 reg = <0x01c01000 0x1000>; 65 clocks = <&ccu CLK_MBUS>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 dma-ranges = <0x00000000 0x40000000 0x20000000>; 69 #interconnect-cells = <1>; 70 }; 71 72... 73