1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/pmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Performance Monitor Units 8 9maintainers: 10 - Mark Rutland <mark.rutland@arm.com> 11 - Will Deacon <will.deacon@arm.com> 12 13description: |+ 14 ARM cores often have a PMU for counting cpu and cache events like cache misses 15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU 16 representation in the device tree should be done as under:- 17 18properties: 19 compatible: 20 items: 21 - enum: 22 - apm,potenza-pmu 23 - arm,armv8-pmuv3 # Only for s/w models 24 - arm,arm1136-pmu 25 - arm,arm1176-pmu 26 - arm,arm11mpcore-pmu 27 - arm,cortex-a5-pmu 28 - arm,cortex-a7-pmu 29 - arm,cortex-a8-pmu 30 - arm,cortex-a9-pmu 31 - arm,cortex-a12-pmu 32 - arm,cortex-a15-pmu 33 - arm,cortex-a17-pmu 34 - arm,cortex-a32-pmu 35 - arm,cortex-a34-pmu 36 - arm,cortex-a35-pmu 37 - arm,cortex-a53-pmu 38 - arm,cortex-a55-pmu 39 - arm,cortex-a57-pmu 40 - arm,cortex-a65-pmu 41 - arm,cortex-a72-pmu 42 - arm,cortex-a73-pmu 43 - arm,cortex-a75-pmu 44 - arm,cortex-a76-pmu 45 - arm,cortex-a77-pmu 46 - arm,neoverse-e1-pmu 47 - arm,neoverse-n1-pmu 48 - brcm,vulcan-pmu 49 - cavium,thunder-pmu 50 - qcom,krait-pmu 51 - qcom,scorpion-pmu 52 - qcom,scorpion-mp-pmu 53 54 interrupts: 55 # Don't know how many CPUs, so no constraints to specify 56 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core. 57 58 interrupt-affinity: 59 $ref: /schemas/types.yaml#/definitions/phandle-array 60 description: 61 When using SPIs, specifies a list of phandles to CPU 62 nodes corresponding directly to the affinity of 63 the SPIs listed in the interrupts property. 64 65 When using a PPI, specifies a list of phandles to CPU 66 nodes corresponding to the set of CPUs which have 67 a PMU of this type signalling the PPI listed in the 68 interrupts property, unless this is already specified 69 by the PPI interrupt specifier itself (in which case 70 the interrupt-affinity property shouldn't be present). 71 72 This property should be present when there is more than 73 a single SPI. 74 75 qcom,no-pc-write: 76 type: boolean 77 description: 78 Indicates that this PMU doesn't support the 0xc and 0xd events. 79 80 secure-reg-access: 81 type: boolean 82 description: 83 Indicates that the ARMv7 Secure Debug Enable Register 84 (SDER) is accessible. This will cause the driver to do 85 any setup required that is only possible in ARMv7 secure 86 state. If not present the ARMv7 SDER will not be touched, 87 which means the PMU may fail to operate unless external 88 code (bootloader or security monitor) has performed the 89 appropriate initialisation. Note that this property is 90 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux 91 in Non-secure state. 92 93required: 94 - compatible 95 96... 97