xref: /freebsd/sys/contrib/device-tree/Bindings/arm/omap/ctrl.txt (revision 6580f5c38dd5b01aeeaed16b370f1a12423437f0)
1OMAP Control Module bindings
2
3Control Module contains miscellaneous features under it based on SoC type.
4Pincontrol is one common feature, and it has a specialized support
5described in [1]. Typically some clock nodes are also under control module.
6Syscon is used to share register level access to drivers external to
7control module driver itself.
8
9See [2] for documentation about clock/clockdomain nodes.
10
11[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
12[2] Documentation/devicetree/bindings/clock/ti/*
13
14Required properties:
15- compatible:	Must be one of:
16		"ti,am3-scm"
17		"ti,am4-scm"
18		"ti,dm814-scrm"
19		"ti,dm816-scrm"
20		"ti,omap2-scm"
21		"ti,omap3-scm"
22		"ti,omap4-scm-core"
23		"ti,omap4-scm-padconf-core"
24		"ti,omap4-scm-wkup"
25		"ti,omap4-scm-padconf-wkup"
26		"ti,omap5-scm-core"
27		"ti,omap5-scm-padconf-core"
28		"ti,omap5-scm-wkup-pad-conf"
29		"ti,dra7-scm-core"
30- reg:		Contains Control Module register address range
31		(base address and length)
32
33Optional properties:
34- clocks:	clocks for this module
35- clockdomains:	clockdomains for this module
36
37Examples:
38
39scm: scm@2000 {
40	compatible = "ti,omap3-scm", "simple-bus";
41	reg = <0x2000 0x2000>;
42	#address-cells = <1>;
43	#size-cells = <1>;
44	ranges = <0 0x2000 0x2000>;
45
46	omap3_pmx_core: pinmux@30 {
47		compatible = "ti,omap3-padconf",
48			     "pinctrl-single";
49		reg = <0x30 0x230>;
50		#address-cells = <1>;
51		#size-cells = <0>;
52		#interrupt-cells = <1>;
53		interrupt-controller;
54		pinctrl-single,register-width = <16>;
55		pinctrl-single,function-mask = <0xff1f>;
56	};
57
58	scm_conf: scm_conf@270 {
59		compatible = "syscon";
60		reg = <0x270 0x330>;
61		#address-cells = <1>;
62		#size-cells = <1>;
63
64		scm_clocks: clocks {
65			#address-cells = <1>;
66			#size-cells = <0>;
67		};
68	};
69
70	scm_clockdomains: clockdomains {
71	};
72}
73
74&scm_clocks {
75	mcbsp5_mux_fck: mcbsp5_mux_fck {
76		#clock-cells = <0>;
77		compatible = "ti,composite-mux-clock";
78		clocks = <&core_96m_fck>, <&mcbsp_clks>;
79		ti,bit-shift = <4>;
80		reg = <0x02d8>;
81	};
82};
83