xref: /freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: MediaTek Functional Clock Controller for MT8195
8
9maintainers:
10  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
11
12description:
13  The clock architecture in Mediatek like below
14  PLLs -->
15          dividers -->
16                      muxes
17                           -->
18                              clock gate
19
20  The devices except apusys_pll provide clock gate control in different IP blocks.
21  The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
22
23properties:
24  compatible:
25    items:
26      - enum:
27          - mediatek,mt8195-scp_adsp
28          - mediatek,mt8195-imp_iic_wrap_s
29          - mediatek,mt8195-imp_iic_wrap_w
30          - mediatek,mt8195-mfgcfg
31          - mediatek,mt8195-vppsys0
32          - mediatek,mt8195-wpesys
33          - mediatek,mt8195-wpesys_vpp0
34          - mediatek,mt8195-wpesys_vpp1
35          - mediatek,mt8195-vppsys1
36          - mediatek,mt8195-imgsys
37          - mediatek,mt8195-imgsys1_dip_top
38          - mediatek,mt8195-imgsys1_dip_nr
39          - mediatek,mt8195-imgsys1_wpe
40          - mediatek,mt8195-ipesys
41          - mediatek,mt8195-camsys
42          - mediatek,mt8195-camsys_rawa
43          - mediatek,mt8195-camsys_yuva
44          - mediatek,mt8195-camsys_rawb
45          - mediatek,mt8195-camsys_yuvb
46          - mediatek,mt8195-camsys_mraw
47          - mediatek,mt8195-ccusys
48          - mediatek,mt8195-vdecsys_soc
49          - mediatek,mt8195-vdecsys
50          - mediatek,mt8195-vdecsys_core1
51          - mediatek,mt8195-vencsys
52          - mediatek,mt8195-vencsys_core1
53          - mediatek,mt8195-apusys_pll
54  reg:
55    maxItems: 1
56
57  '#clock-cells':
58    const: 1
59
60required:
61  - compatible
62  - reg
63
64additionalProperties: false
65
66examples:
67  - |
68    scp_adsp: clock-controller@10720000 {
69        compatible = "mediatek,mt8195-scp_adsp";
70        reg = <0x10720000 0x1000>;
71        #clock-cells = <1>;
72    };
73
74  - |
75    imp_iic_wrap_s: clock-controller@11d03000 {
76        compatible = "mediatek,mt8195-imp_iic_wrap_s";
77        reg = <0x11d03000 0x1000>;
78        #clock-cells = <1>;
79    };
80
81  - |
82    imp_iic_wrap_w: clock-controller@11e05000 {
83        compatible = "mediatek,mt8195-imp_iic_wrap_w";
84        reg = <0x11e05000 0x1000>;
85        #clock-cells = <1>;
86    };
87
88  - |
89    mfgcfg: clock-controller@13fbf000 {
90        compatible = "mediatek,mt8195-mfgcfg";
91        reg = <0x13fbf000 0x1000>;
92        #clock-cells = <1>;
93    };
94
95  - |
96    vppsys0: clock-controller@14000000 {
97        compatible = "mediatek,mt8195-vppsys0";
98        reg = <0x14000000 0x1000>;
99        #clock-cells = <1>;
100    };
101
102  - |
103    wpesys: clock-controller@14e00000 {
104        compatible = "mediatek,mt8195-wpesys";
105        reg = <0x14e00000 0x1000>;
106        #clock-cells = <1>;
107    };
108
109  - |
110    wpesys_vpp0: clock-controller@14e02000 {
111        compatible = "mediatek,mt8195-wpesys_vpp0";
112        reg = <0x14e02000 0x1000>;
113        #clock-cells = <1>;
114    };
115
116  - |
117    wpesys_vpp1: clock-controller@14e03000 {
118        compatible = "mediatek,mt8195-wpesys_vpp1";
119        reg = <0x14e03000 0x1000>;
120        #clock-cells = <1>;
121    };
122
123  - |
124    vppsys1: clock-controller@14f00000 {
125        compatible = "mediatek,mt8195-vppsys1";
126        reg = <0x14f00000 0x1000>;
127        #clock-cells = <1>;
128    };
129
130  - |
131    imgsys: clock-controller@15000000 {
132        compatible = "mediatek,mt8195-imgsys";
133        reg = <0x15000000 0x1000>;
134        #clock-cells = <1>;
135    };
136
137  - |
138    imgsys1_dip_top: clock-controller@15110000 {
139        compatible = "mediatek,mt8195-imgsys1_dip_top";
140        reg = <0x15110000 0x1000>;
141        #clock-cells = <1>;
142    };
143
144  - |
145    imgsys1_dip_nr: clock-controller@15130000 {
146        compatible = "mediatek,mt8195-imgsys1_dip_nr";
147        reg = <0x15130000 0x1000>;
148        #clock-cells = <1>;
149    };
150
151  - |
152    imgsys1_wpe: clock-controller@15220000 {
153        compatible = "mediatek,mt8195-imgsys1_wpe";
154        reg = <0x15220000 0x1000>;
155        #clock-cells = <1>;
156    };
157
158  - |
159    ipesys: clock-controller@15330000 {
160        compatible = "mediatek,mt8195-ipesys";
161        reg = <0x15330000 0x1000>;
162        #clock-cells = <1>;
163    };
164
165  - |
166    camsys: clock-controller@16000000 {
167        compatible = "mediatek,mt8195-camsys";
168        reg = <0x16000000 0x1000>;
169        #clock-cells = <1>;
170    };
171
172  - |
173    camsys_rawa: clock-controller@1604f000 {
174        compatible = "mediatek,mt8195-camsys_rawa";
175        reg = <0x1604f000 0x1000>;
176        #clock-cells = <1>;
177    };
178
179  - |
180    camsys_yuva: clock-controller@1606f000 {
181        compatible = "mediatek,mt8195-camsys_yuva";
182        reg = <0x1606f000 0x1000>;
183        #clock-cells = <1>;
184    };
185
186  - |
187    camsys_rawb: clock-controller@1608f000 {
188        compatible = "mediatek,mt8195-camsys_rawb";
189        reg = <0x1608f000 0x1000>;
190        #clock-cells = <1>;
191    };
192
193  - |
194    camsys_yuvb: clock-controller@160af000 {
195        compatible = "mediatek,mt8195-camsys_yuvb";
196        reg = <0x160af000 0x1000>;
197        #clock-cells = <1>;
198    };
199
200  - |
201    camsys_mraw: clock-controller@16140000 {
202        compatible = "mediatek,mt8195-camsys_mraw";
203        reg = <0x16140000 0x1000>;
204        #clock-cells = <1>;
205    };
206
207  - |
208    ccusys: clock-controller@17200000 {
209        compatible = "mediatek,mt8195-ccusys";
210        reg = <0x17200000 0x1000>;
211        #clock-cells = <1>;
212    };
213
214  - |
215    vdecsys_soc: clock-controller@1800f000 {
216        compatible = "mediatek,mt8195-vdecsys_soc";
217        reg = <0x1800f000 0x1000>;
218        #clock-cells = <1>;
219    };
220
221  - |
222    vdecsys: clock-controller@1802f000 {
223        compatible = "mediatek,mt8195-vdecsys";
224        reg = <0x1802f000 0x1000>;
225        #clock-cells = <1>;
226    };
227
228  - |
229    vdecsys_core1: clock-controller@1803f000 {
230        compatible = "mediatek,mt8195-vdecsys_core1";
231        reg = <0x1803f000 0x1000>;
232        #clock-cells = <1>;
233    };
234
235  - |
236    vencsys: clock-controller@1a000000 {
237        compatible = "mediatek,mt8195-vencsys";
238        reg = <0x1a000000 0x1000>;
239        #clock-cells = <1>;
240    };
241
242  - |
243    vencsys_core1: clock-controller@1b000000 {
244        compatible = "mediatek,mt8195-vencsys_core1";
245        reg = <0x1b000000 0x1000>;
246        #clock-cells = <1>;
247    };
248
249  - |
250    apusys_pll: clock-controller@190f3000 {
251        compatible = "mediatek,mt8195-apusys_pll";
252        reg = <0x190f3000 0x1000>;
253        #clock-cells = <1>;
254    };
255