xref: /freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mmsys.yaml (revision 95eb4b873b6a8b527c5bd78d7191975dfca38998) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek mmsys controller
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11
12description:
13  The MediaTek mmsys system controller provides clock control, routing control,
14  and miscellaneous control in mmsys partition.
15
16properties:
17  $nodename:
18    pattern: "^syscon@[0-9a-f]+$"
19
20  compatible:
21    oneOf:
22      - items:
23          - enum:
24              - mediatek,mt2701-mmsys
25              - mediatek,mt2712-mmsys
26              - mediatek,mt6765-mmsys
27              - mediatek,mt6779-mmsys
28              - mediatek,mt6795-mmsys
29              - mediatek,mt6797-mmsys
30              - mediatek,mt8167-mmsys
31              - mediatek,mt8173-mmsys
32              - mediatek,mt8183-mmsys
33              - mediatek,mt8186-mmsys
34              - mediatek,mt8188-vdosys0
35              - mediatek,mt8188-vdosys1
36              - mediatek,mt8188-vppsys0
37              - mediatek,mt8188-vppsys1
38              - mediatek,mt8192-mmsys
39              - mediatek,mt8195-vdosys1
40              - mediatek,mt8195-vppsys0
41              - mediatek,mt8195-vppsys1
42              - mediatek,mt8365-mmsys
43          - const: syscon
44
45      - description: vdosys0 and vdosys1 are 2 display HW pipelines,
46                     so mt8195 binding should be deprecated.
47        deprecated: true
48        items:
49          - const: mediatek,mt8195-mmsys
50          - const: syscon
51
52      - items:
53          - const: mediatek,mt7623-mmsys
54          - const: mediatek,mt2701-mmsys
55          - const: syscon
56
57      - items:
58          - const: mediatek,mt8195-vdosys0
59          - const: mediatek,mt8195-mmsys
60          - const: syscon
61
62  reg:
63    maxItems: 1
64
65  power-domains:
66    description:
67      A phandle and PM domain specifier as defined by bindings
68      of the power controller specified by phandle. See
69      Documentation/devicetree/bindings/power/power-domain.yaml for details.
70
71  mboxes:
72    description:
73      Using mailbox to communicate with GCE, it should have this
74      property and list of phandle, mailbox specifiers. See
75      Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
76      for details.
77    $ref: /schemas/types.yaml#/definitions/phandle-array
78
79  mediatek,gce-client-reg:
80    description:
81      The register of client driver can be configured by gce with 4 arguments
82      defined in this property, such as phandle of gce, subsys id,
83      register offset and size.
84      Each subsys id is mapping to a base address of display function blocks
85      register which is defined in the gce header
86      include/dt-bindings/gce/<chip>-gce.h.
87    $ref: /schemas/types.yaml#/definitions/phandle-array
88    maxItems: 1
89
90  "#clock-cells":
91    const: 1
92
93  '#reset-cells':
94    const: 1
95
96required:
97  - compatible
98  - reg
99  - "#clock-cells"
100
101additionalProperties: false
102
103examples:
104  - |
105    #include <dt-bindings/power/mt8173-power.h>
106    #include <dt-bindings/gce/mt8173-gce.h>
107
108    mmsys: syscon@14000000 {
109        compatible = "mediatek,mt8173-mmsys", "syscon";
110        reg = <0x14000000 0x1000>;
111        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
112        #clock-cells = <1>;
113        #reset-cells = <1>;
114        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
115                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
116        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
117    };
118