xref: /freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mmsys.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek mmsys controller
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11
12description:
13  The MediaTek mmsys system controller provides clock control, routing control,
14  and miscellaneous control in mmsys partition.
15
16properties:
17  $nodename:
18    pattern: "^syscon@[0-9a-f]+$"
19
20  compatible:
21    oneOf:
22      - items:
23          - enum:
24              - mediatek,mt2701-mmsys
25              - mediatek,mt2712-mmsys
26              - mediatek,mt6765-mmsys
27              - mediatek,mt6779-mmsys
28              - mediatek,mt6795-mmsys
29              - mediatek,mt6797-mmsys
30              - mediatek,mt8167-mmsys
31              - mediatek,mt8173-mmsys
32              - mediatek,mt8183-mmsys
33              - mediatek,mt8186-mmsys
34              - mediatek,mt8188-vdosys0
35              - mediatek,mt8192-mmsys
36              - mediatek,mt8195-vdosys1
37              - mediatek,mt8195-vppsys0
38              - mediatek,mt8195-vppsys1
39              - mediatek,mt8365-mmsys
40          - const: syscon
41
42      - description: vdosys0 and vdosys1 are 2 display HW pipelines,
43                     so mt8195 binding should be deprecated.
44        deprecated: true
45        items:
46          - const: mediatek,mt8195-mmsys
47          - const: syscon
48
49      - items:
50          - const: mediatek,mt7623-mmsys
51          - const: mediatek,mt2701-mmsys
52          - const: syscon
53
54      - items:
55          - const: mediatek,mt8195-vdosys0
56          - const: mediatek,mt8195-mmsys
57          - const: syscon
58
59  reg:
60    maxItems: 1
61
62  power-domains:
63    description:
64      A phandle and PM domain specifier as defined by bindings
65      of the power controller specified by phandle. See
66      Documentation/devicetree/bindings/power/power-domain.yaml for details.
67
68  mboxes:
69    description:
70      Using mailbox to communicate with GCE, it should have this
71      property and list of phandle, mailbox specifiers. See
72      Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
73      for details.
74    $ref: /schemas/types.yaml#/definitions/phandle-array
75
76  mediatek,gce-client-reg:
77    description:
78      The register of client driver can be configured by gce with 4 arguments
79      defined in this property, such as phandle of gce, subsys id,
80      register offset and size.
81      Each subsys id is mapping to a base address of display function blocks
82      register which is defined in the gce header
83      include/dt-bindings/gce/<chip>-gce.h.
84    $ref: /schemas/types.yaml#/definitions/phandle-array
85    maxItems: 1
86
87  "#clock-cells":
88    const: 1
89
90  '#reset-cells':
91    const: 1
92
93required:
94  - compatible
95  - reg
96  - "#clock-cells"
97
98additionalProperties: false
99
100examples:
101  - |
102    #include <dt-bindings/power/mt8173-power.h>
103    #include <dt-bindings/gce/mt8173-gce.h>
104
105    mmsys: syscon@14000000 {
106        compatible = "mediatek,mt8173-mmsys", "syscon";
107        reg = <0x14000000 0x1000>;
108        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
109        #clock-cells = <1>;
110        #reset-cells = <1>;
111        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
112                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
113        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
114    };
115