1*c66ec88fSEmmanuel VadotMediatek IPU controller 2*c66ec88fSEmmanuel Vadot============================ 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotThe Mediatek ipu controller provides various clocks to the system. 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel VadotRequired Properties: 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot- compatible: Should be one of: 9*c66ec88fSEmmanuel Vadot - "mediatek,mt8183-ipu_conn", "syscon" 10*c66ec88fSEmmanuel Vadot - "mediatek,mt8183-ipu_adl", "syscon" 11*c66ec88fSEmmanuel Vadot - "mediatek,mt8183-ipu_core0", "syscon" 12*c66ec88fSEmmanuel Vadot - "mediatek,mt8183-ipu_core1", "syscon" 13*c66ec88fSEmmanuel Vadot- #clock-cells: Must be 1 14*c66ec88fSEmmanuel Vadot 15*c66ec88fSEmmanuel VadotThe ipu controller uses the common clk binding from 16*c66ec88fSEmmanuel VadotDocumentation/devicetree/bindings/clock/clock-bindings.txt 17*c66ec88fSEmmanuel VadotThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel VadotExample: 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel Vadotipu_conn: syscon@19000000 { 22*c66ec88fSEmmanuel Vadot compatible = "mediatek,mt8183-ipu_conn", "syscon"; 23*c66ec88fSEmmanuel Vadot reg = <0 0x19000000 0 0x1000>; 24*c66ec88fSEmmanuel Vadot #clock-cells = <1>; 25*c66ec88fSEmmanuel Vadot}; 26*c66ec88fSEmmanuel Vadot 27*c66ec88fSEmmanuel Vadotipu_adl: syscon@19010000 { 28*c66ec88fSEmmanuel Vadot compatible = "mediatek,mt8183-ipu_adl", "syscon"; 29*c66ec88fSEmmanuel Vadot reg = <0 0x19010000 0 0x1000>; 30*c66ec88fSEmmanuel Vadot #clock-cells = <1>; 31*c66ec88fSEmmanuel Vadot}; 32*c66ec88fSEmmanuel Vadot 33*c66ec88fSEmmanuel Vadotipu_core0: syscon@19180000 { 34*c66ec88fSEmmanuel Vadot compatible = "mediatek,mt8183-ipu_core0", "syscon"; 35*c66ec88fSEmmanuel Vadot reg = <0 0x19180000 0 0x1000>; 36*c66ec88fSEmmanuel Vadot #clock-cells = <1>; 37*c66ec88fSEmmanuel Vadot}; 38*c66ec88fSEmmanuel Vadot 39*c66ec88fSEmmanuel Vadotipu_core1: syscon@19280000 { 40*c66ec88fSEmmanuel Vadot compatible = "mediatek,mt8183-ipu_core1", "syscon"; 41*c66ec88fSEmmanuel Vadot reg = <0 0x19280000 0 0x1000>; 42*c66ec88fSEmmanuel Vadot #clock-cells = <1>; 43*c66ec88fSEmmanuel Vadot}; 44