1Mediatek infracfg controller 2============================ 3 4The Mediatek infracfg controller provides various clocks and reset 5outputs to the system. 6 7Required Properties: 8 9- compatible: Should be one of: 10 - "mediatek,mt2701-infracfg", "syscon" 11 - "mediatek,mt2712-infracfg", "syscon" 12 - "mediatek,mt6765-infracfg", "syscon" 13 - "mediatek,mt6779-infracfg_ao", "syscon" 14 - "mediatek,mt6797-infracfg", "syscon" 15 - "mediatek,mt7622-infracfg", "syscon" 16 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" 17 - "mediatek,mt7629-infracfg", "syscon" 18 - "mediatek,mt7986-infracfg", "syscon" 19 - "mediatek,mt8135-infracfg", "syscon" 20 - "mediatek,mt8167-infracfg", "syscon" 21 - "mediatek,mt8173-infracfg", "syscon" 22 - "mediatek,mt8183-infracfg", "syscon" 23 - "mediatek,mt8516-infracfg", "syscon" 24- #clock-cells: Must be 1 25- #reset-cells: Must be 1 26 27The infracfg controller uses the common clk binding from 28Documentation/devicetree/bindings/clock/clock-bindings.txt 29The available clocks are defined in dt-bindings/clock/mt*-clk.h. 30Also it uses the common reset controller binding from 31Documentation/devicetree/bindings/reset/reset.txt. 32The available reset outputs are defined in 33dt-bindings/reset/mt*-resets.h 34 35Example: 36 37infracfg: power-controller@10001000 { 38 compatible = "mediatek,mt8173-infracfg", "syscon"; 39 reg = <0 0x10001000 0 0x1000>; 40 #clock-cells = <1>; 41 #reset-cells = <1>; 42}; 43