1*c66ec88fSEmmanuel VadotMediatek hifsys controller 2*c66ec88fSEmmanuel Vadot============================ 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotThe Mediatek hifsys controller provides various clocks and reset 5*c66ec88fSEmmanuel Vadotoutputs to the system. 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotRequired Properties: 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot- compatible: Should be: 10*c66ec88fSEmmanuel Vadot - "mediatek,mt2701-hifsys", "syscon" 11*c66ec88fSEmmanuel Vadot - "mediatek,mt7622-hifsys", "syscon" 12*c66ec88fSEmmanuel Vadot - "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", "syscon" 13*c66ec88fSEmmanuel Vadot- #clock-cells: Must be 1 14*c66ec88fSEmmanuel Vadot 15*c66ec88fSEmmanuel VadotThe hifsys controller uses the common clk binding from 16*c66ec88fSEmmanuel VadotDocumentation/devicetree/bindings/clock/clock-bindings.txt 17*c66ec88fSEmmanuel VadotThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel VadotExample: 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel Vadothifsys: clock-controller@1a000000 { 22*c66ec88fSEmmanuel Vadot compatible = "mediatek,mt2701-hifsys", "syscon"; 23*c66ec88fSEmmanuel Vadot reg = <0 0x1a000000 0 0x1000>; 24*c66ec88fSEmmanuel Vadot #clock-cells = <1>; 25*c66ec88fSEmmanuel Vadot #reset-cells = <1>; 26*c66ec88fSEmmanuel Vadot}; 27