1c66ec88fSEmmanuel VadotMediatek ethsys controller 2c66ec88fSEmmanuel Vadot============================ 3c66ec88fSEmmanuel Vadot 4c66ec88fSEmmanuel VadotThe Mediatek ethsys controller provides various clocks to the system. 5c66ec88fSEmmanuel Vadot 6c66ec88fSEmmanuel VadotRequired Properties: 7c66ec88fSEmmanuel Vadot 8c66ec88fSEmmanuel Vadot- compatible: Should be: 9c66ec88fSEmmanuel Vadot - "mediatek,mt2701-ethsys", "syscon" 10c66ec88fSEmmanuel Vadot - "mediatek,mt7622-ethsys", "syscon" 11c66ec88fSEmmanuel Vadot - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" 12c66ec88fSEmmanuel Vadot - "mediatek,mt7629-ethsys", "syscon" 13*cb7aa33aSEmmanuel Vadot - "mediatek,mt7981-ethsys", "syscon" 14e67e8565SEmmanuel Vadot - "mediatek,mt7986-ethsys", "syscon" 15c66ec88fSEmmanuel Vadot- #clock-cells: Must be 1 16c66ec88fSEmmanuel Vadot- #reset-cells: Must be 1 17c66ec88fSEmmanuel Vadot 18c66ec88fSEmmanuel VadotThe ethsys controller uses the common clk binding from 19c66ec88fSEmmanuel VadotDocumentation/devicetree/bindings/clock/clock-bindings.txt 20c66ec88fSEmmanuel VadotThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 21c66ec88fSEmmanuel Vadot 22c66ec88fSEmmanuel VadotExample: 23c66ec88fSEmmanuel Vadot 24c66ec88fSEmmanuel Vadotethsys: clock-controller@1b000000 { 25c66ec88fSEmmanuel Vadot compatible = "mediatek,mt2701-ethsys", "syscon"; 26c66ec88fSEmmanuel Vadot reg = <0 0x1b000000 0 0x1000>; 27c66ec88fSEmmanuel Vadot #clock-cells = <1>; 28c66ec88fSEmmanuel Vadot #reset-cells = <1>; 29c66ec88fSEmmanuel Vadot}; 30