xref: /freebsd/sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,audsys.yaml (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0)

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek AUDSYS controller

maintainers:
  - Eugen Hristev <eugen.hristev@collabora.com>

description:
  The MediaTek AUDSYS controller provides various clocks to the system.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt2701-audsys
              - mediatek,mt6765-audsys
              - mediatek,mt6779-audsys
              - mediatek,mt7622-audsys
              - mediatek,mt8167-audsys
              - mediatek,mt8173-audsys
              - mediatek,mt8183-audsys
              - mediatek,mt8186-audsys
              - mediatek,mt8192-audsys
              - mediatek,mt8516-audsys
          - const: syscon
      - items:
          # Special case for mt7623 for backward compatibility
          - const: mediatek,mt7623-audsys
          - const: mediatek,mt2701-audsys
          - const: syscon

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  audio-controller:
    $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
    type: object

required:
  - compatible
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/power/mt2701-power.h>
    #include <dt-bindings/clock/mt2701-clk.h>
    soc {
        #address-cells = <2>;
        #size-cells = <2>;
        audsys: clock-controller@11220000 {
            compatible = "mediatek,mt7622-audsys", "syscon";
            reg = <0 0x11220000 0 0x2000>;
            #clock-cells = <1>;

            afe: audio-controller {
                compatible = "mediatek,mt2701-audio";
                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
                             <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
                interrupt-names = "afe", "asys";
                power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;

                clocks = <&infracfg CLK_INFRA_AUDIO>,
                         <&topckgen CLK_TOP_AUD_MUX1_SEL>,
                         <&topckgen CLK_TOP_AUD_MUX2_SEL>,
                         <&topckgen CLK_TOP_AUD_48K_TIMING>,
                         <&topckgen CLK_TOP_AUD_44K_TIMING>,
                         <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
                         <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
                         <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
                         <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
                         <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
                         <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
                         <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
                         <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
                         <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
                         <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
                         <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
                         <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
                         <&audsys CLK_AUD_I2SO1>,
                         <&audsys CLK_AUD_I2SO2>,
                         <&audsys CLK_AUD_I2SO3>,
                         <&audsys CLK_AUD_I2SO4>,
                         <&audsys CLK_AUD_I2SIN1>,
                         <&audsys CLK_AUD_I2SIN2>,
                         <&audsys CLK_AUD_I2SIN3>,
                         <&audsys CLK_AUD_I2SIN4>,
                         <&audsys CLK_AUD_ASRCO1>,
                         <&audsys CLK_AUD_ASRCO2>,
                         <&audsys CLK_AUD_ASRCO3>,
                         <&audsys CLK_AUD_ASRCO4>,
                         <&audsys CLK_AUD_AFE>,
                         <&audsys CLK_AUD_AFE_CONN>,
                         <&audsys CLK_AUD_A1SYS>,
                         <&audsys CLK_AUD_A2SYS>,
                         <&audsys CLK_AUD_AFE_MRGIF>;

                clock-names = "infra_sys_audio_clk",
                              "top_audio_mux1_sel",
                              "top_audio_mux2_sel",
                              "top_audio_a1sys_hp",
                              "top_audio_a2sys_hp",
                              "i2s0_src_sel",
                              "i2s1_src_sel",
                              "i2s2_src_sel",
                              "i2s3_src_sel",
                              "i2s0_src_div",
                              "i2s1_src_div",
                              "i2s2_src_div",
                              "i2s3_src_div",
                              "i2s0_mclk_en",
                              "i2s1_mclk_en",
                              "i2s2_mclk_en",
                              "i2s3_mclk_en",
                              "i2so0_hop_ck",
                              "i2so1_hop_ck",
                              "i2so2_hop_ck",
                              "i2so3_hop_ck",
                              "i2si0_hop_ck",
                              "i2si1_hop_ck",
                              "i2si2_hop_ck",
                              "i2si3_hop_ck",
                              "asrc0_out_ck",
                              "asrc1_out_ck",
                              "asrc2_out_ck",
                              "asrc3_out_ck",
                              "audio_afe_pd",
                              "audio_afe_conn_pd",
                              "audio_a1sys_pd",
                              "audio_a2sys_pd",
                              "audio_mrgif_pd";

                assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
                                  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
                                  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
                                  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
                assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
                                         <&topckgen CLK_TOP_AUD2PLL_90M>;
                assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
            };
        };
    };