1c66ec88fSEmmanuel VadotMediatek mfgcfg controller 2c66ec88fSEmmanuel Vadot============================ 3c66ec88fSEmmanuel Vadot 4c66ec88fSEmmanuel VadotThe Mediatek mfgcfg controller provides various clocks to the system. 5c66ec88fSEmmanuel Vadot 6c66ec88fSEmmanuel VadotRequired Properties: 7c66ec88fSEmmanuel Vadot 8c66ec88fSEmmanuel Vadot- compatible: Should be one of: 9c66ec88fSEmmanuel Vadot - "mediatek,mt2712-mfgcfg", "syscon" 10c66ec88fSEmmanuel Vadot - "mediatek,mt6779-mfgcfg", "syscon" 11*6be33864SEmmanuel Vadot - "mediatek,mt8167-mfgcfg", "syscon" 12c66ec88fSEmmanuel Vadot - "mediatek,mt8183-mfgcfg", "syscon" 13c66ec88fSEmmanuel Vadot- #clock-cells: Must be 1 14c66ec88fSEmmanuel Vadot 15c66ec88fSEmmanuel VadotThe mfgcfg controller uses the common clk binding from 16c66ec88fSEmmanuel VadotDocumentation/devicetree/bindings/clock/clock-bindings.txt 17c66ec88fSEmmanuel VadotThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 18c66ec88fSEmmanuel Vadot 19c66ec88fSEmmanuel VadotExample: 20c66ec88fSEmmanuel Vadot 21c66ec88fSEmmanuel Vadotmfgcfg: syscon@13000000 { 22c66ec88fSEmmanuel Vadot compatible = "mediatek,mt2712-mfgcfg", "syscon"; 23c66ec88fSEmmanuel Vadot reg = <0 0x13000000 0 0x1000>; 24c66ec88fSEmmanuel Vadot #clock-cells = <1>; 25c66ec88fSEmmanuel Vadot}; 26