1*c66ec88fSEmmanuel VadotMediatek ethsys controller 2*c66ec88fSEmmanuel Vadot============================ 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotThe Mediatek ethsys controller provides various clocks to the system. 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel VadotRequired Properties: 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot- compatible: Should be: 9*c66ec88fSEmmanuel Vadot - "mediatek,mt2701-ethsys", "syscon" 10*c66ec88fSEmmanuel Vadot - "mediatek,mt7622-ethsys", "syscon" 11*c66ec88fSEmmanuel Vadot - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon" 12*c66ec88fSEmmanuel Vadot - "mediatek,mt7629-ethsys", "syscon" 13*c66ec88fSEmmanuel Vadot- #clock-cells: Must be 1 14*c66ec88fSEmmanuel Vadot- #reset-cells: Must be 1 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel VadotThe ethsys controller uses the common clk binding from 17*c66ec88fSEmmanuel VadotDocumentation/devicetree/bindings/clock/clock-bindings.txt 18*c66ec88fSEmmanuel VadotThe available clocks are defined in dt-bindings/clock/mt*-clk.h. 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel VadotExample: 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel Vadotethsys: clock-controller@1b000000 { 23*c66ec88fSEmmanuel Vadot compatible = "mediatek,mt2701-ethsys", "syscon"; 24*c66ec88fSEmmanuel Vadot reg = <0 0x1b000000 0 0x1000>; 25*c66ec88fSEmmanuel Vadot #clock-cells = <1>; 26*c66ec88fSEmmanuel Vadot #reset-cells = <1>; 27*c66ec88fSEmmanuel Vadot}; 28