1Hisilicon Platforms Device Tree Bindings 2---------------------------------------------------- 3Hi3660 SoC 4Required root node properties: 5 - compatible = "hisilicon,hi3660"; 6 7HiKey960 Board 8Required root node properties: 9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; 10 11Hi3670 SoC 12Required root node properties: 13 - compatible = "hisilicon,hi3670"; 14 15HiKey970 Board 16Required root node properties: 17 - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; 18 19Hi3798cv200 SoC 20Required root node properties: 21 - compatible = "hisilicon,hi3798cv200"; 22 23Hi3798cv200 Poplar Board 24Required root node properties: 25 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; 26 27Hi4511 Board 28Required root node properties: 29 - compatible = "hisilicon,hi3620-hi4511"; 30 31Hi6220 SoC 32Required root node properties: 33 - compatible = "hisilicon,hi6220"; 34 35HiKey Board 36Required root node properties: 37 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; 38 39HiP01 ca9x2 Board 40Required root node properties: 41 - compatible = "hisilicon,hip01-ca9x2"; 42 43HiP04 D01 Board 44Required root node properties: 45 - compatible = "hisilicon,hip04-d01"; 46 47HiP05 D02 Board 48Required root node properties: 49 - compatible = "hisilicon,hip05-d02"; 50 51HiP06 D03 Board 52Required root node properties: 53 - compatible = "hisilicon,hip06-d03"; 54 55HiP07 D05 Board 56Required root node properties: 57 - compatible = "hisilicon,hip07-d05"; 58 59Hisilicon system controller 60 61Required properties: 62- compatible : "hisilicon,sysctrl" 63- reg : Register address and size 64 65Optional properties: 66- smp-offset : offset in sysctrl for notifying slave cpu booting 67 cpu 1, reg; 68 cpu 2, reg + 0x4; 69 cpu 3, reg + 0x8; 70 If reg value is not zero, cpun exit wfi and go 71- resume-offset : offset in sysctrl for notifying cpu0 when resume 72- reboot-offset : offset in sysctrl for system reboot 73 74Example: 75 76 /* for Hi3620 */ 77 sysctrl: system-controller@fc802000 { 78 compatible = "hisilicon,sysctrl"; 79 reg = <0xfc802000 0x1000>; 80 smp-offset = <0x31c>; 81 resume-offset = <0x308>; 82 reboot-offset = <0x4>; 83 }; 84 85----------------------------------------------------------------------- 86Hisilicon Hi3798CV200 Peripheral Controller 87 88The Hi3798CV200 Peripheral Controller controls peripherals, queries 89their status, and configures some functions of peripherals. 90 91Required properties: 92- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" 93 and "simple-mfd". 94- reg: Register address and size of Peripheral Controller. 95- #address-cells: Should be 1. 96- #size-cells: Should be 1. 97 98Examples: 99 100 perictrl: peripheral-controller@8a20000 { 101 compatible = "hisilicon,hi3798cv200-perictrl", "syscon", 102 "simple-mfd"; 103 reg = <0x8a20000 0x1000>; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 }; 107 108----------------------------------------------------------------------- 109Hisilicon Hi6220 system controller 110 111Required properties: 112- compatible : "hisilicon,hi6220-sysctrl" 113- reg : Register address and size 114- #clock-cells: should be set to 1, many clock registers are defined 115 under this controller and this property must be present. 116 117Hisilicon designs this controller as one of the system controllers, 118its main functions are the same as Hisilicon system controller, but 119the register offset of some core modules are different. 120 121Example: 122 /*for Hi6220*/ 123 sys_ctrl: sys_ctrl@f7030000 { 124 compatible = "hisilicon,hi6220-sysctrl", "syscon"; 125 reg = <0x0 0xf7030000 0x0 0x2000>; 126 #clock-cells = <1>; 127 }; 128 129 130Hisilicon Hi6220 Power Always ON domain controller 131 132Required properties: 133- compatible : "hisilicon,hi6220-aoctrl" 134- reg : Register address and size 135- #clock-cells: should be set to 1, many clock registers are defined 136 under this controller and this property must be present. 137 138Hisilicon designs this system controller to control the power always 139on domain for mobile platform. 140 141Example: 142 /*for Hi6220*/ 143 ao_ctrl: ao_ctrl@f7800000 { 144 compatible = "hisilicon,hi6220-aoctrl", "syscon"; 145 reg = <0x0 0xf7800000 0x0 0x2000>; 146 #clock-cells = <1>; 147 }; 148 149 150Hisilicon Hi6220 Media domain controller 151 152Required properties: 153- compatible : "hisilicon,hi6220-mediactrl" 154- reg : Register address and size 155- #clock-cells: should be set to 1, many clock registers are defined 156 under this controller and this property must be present. 157 158Hisilicon designs this system controller to control the multimedia 159domain(e.g. codec, G3D ...) for mobile platform. 160 161Example: 162 /*for Hi6220*/ 163 media_ctrl: media_ctrl@f4410000 { 164 compatible = "hisilicon,hi6220-mediactrl", "syscon"; 165 reg = <0x0 0xf4410000 0x0 0x1000>; 166 #clock-cells = <1>; 167 }; 168 169 170Hisilicon Hi6220 Power Management domain controller 171 172Required properties: 173- compatible : "hisilicon,hi6220-pmctrl" 174- reg : Register address and size 175- #clock-cells: should be set to 1, some clock registers are define 176 under this controller and this property must be present. 177 178Hisilicon designs this system controller to control the power management 179domain for mobile platform. 180 181Example: 182 /*for Hi6220*/ 183 pm_ctrl: pm_ctrl@f7032000 { 184 compatible = "hisilicon,hi6220-pmctrl", "syscon"; 185 reg = <0x0 0xf7032000 0x0 0x1000>; 186 #clock-cells = <1>; 187 }; 188 189 190Hisilicon Hi6220 SRAM controller 191 192Required properties: 193- compatible : "hisilicon,hi6220-sramctrl", "syscon" 194- reg : Register address and size 195 196Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several 197SRAM banks for power management, modem, security, etc. Further, use "syscon" 198managing the common sram which can be shared by multiple modules. 199 200Example: 201 /*for Hi6220*/ 202 sram: sram@fff80000 { 203 compatible = "hisilicon,hi6220-sramctrl", "syscon"; 204 reg = <0x0 0xfff80000 0x0 0x12000>; 205 }; 206 207----------------------------------------------------------------------- 208Hisilicon HiP01 system controller 209 210Required properties: 211- compatible : "hisilicon,hip01-sysctrl" 212- reg : Register address and size 213 214The HiP01 system controller is mostly compatible with hisilicon 215system controller,but it has some specific control registers for 216HIP01 SoC family, such as slave core boot, and also some same 217registers located at different offset. 218 219Example: 220 221 /* for hip01-ca9x2 */ 222 sysctrl: system-controller@10000000 { 223 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; 224 reg = <0x10000000 0x1000>; 225 reboot-offset = <0x4>; 226 }; 227 228----------------------------------------------------------------------- 229Hisilicon HiP05/HiP06 PCIe-SAS sub system controller 230 231Required properties: 232- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; 233- reg : Register address and size 234 235The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in 236HiP05 or HiP06 Soc to implement some basic configurations. 237 238Example: 239 /* for HiP05 PCIe-SAS sub system */ 240 pcie_sas: system_controller@b0000000 { 241 compatible = "hisilicon,pcie-sas-subctrl", "syscon"; 242 reg = <0xb0000000 0x10000>; 243 }; 244 245Hisilicon HiP05/HiP06 PERI sub system controller 246 247Required properties: 248- compatible : "hisilicon,peri-subctrl", "syscon"; 249- reg : Register address and size 250 251The PERI sub system controller is shared by peripheral controllers in 252HiP05 or HiP06 Soc to implement some basic configurations. The peripheral 253controllers include mdio, ddr, iic, uart, timer and so on. 254 255Example: 256 /* for HiP05 sub peri system */ 257 peri_c_subctrl: syscon@80000000 { 258 compatible = "hisilicon,peri-subctrl", "syscon"; 259 reg = <0x0 0x80000000 0x0 0x10000>; 260 }; 261 262Hisilicon HiP05/HiP06 DSA sub system controller 263 264Required properties: 265- compatible : "hisilicon,dsa-subctrl", "syscon"; 266- reg : Register address and size 267 268The DSA sub system controller is shared by peripheral controllers in 269HiP05 or HiP06 Soc to implement some basic configurations. 270 271Example: 272 /* for HiP05 dsa sub system */ 273 pcie_sas: system_controller@a0000000 { 274 compatible = "hisilicon,dsa-subctrl", "syscon"; 275 reg = <0xa0000000 0x10000>; 276 }; 277 278----------------------------------------------------------------------- 279Hisilicon CPU controller 280 281Required properties: 282- compatible : "hisilicon,cpuctrl" 283- reg : Register address and size 284 285The clock registers and power registers of secondary cores are defined 286in CPU controller, especially in HIX5HD2 SoC. 287 288----------------------------------------------------------------------- 289PCTRL: Peripheral misc control register 290 291Required Properties: 292- compatible: "hisilicon,pctrl" 293- reg: Address and size of pctrl. 294 295Example: 296 297 /* for Hi3620 */ 298 pctrl: pctrl@fca09000 { 299 compatible = "hisilicon,pctrl"; 300 reg = <0xfca09000 0x1000>; 301 }; 302 303----------------------------------------------------------------------- 304Fabric: 305 306Required Properties: 307- compatible: "hisilicon,hip04-fabric"; 308- reg: Address and size of Fabric 309 310----------------------------------------------------------------------- 311Bootwrapper boot method (software protocol on SMP): 312 313Required Properties: 314- compatible: "hisilicon,hip04-bootwrapper"; 315- boot-method: Address and size of boot method. 316 [0]: bootwrapper physical address 317 [1]: bootwrapper size 318 [2]: relocation physical address 319 [3]: relocation size 320