1Hisilicon Hip06 Low Pin Count device 2 Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which 3 provides I/O access to some legacy ISA devices. 4 Hip06 is based on arm64 architecture where there is no I/O space. So, the 5 I/O ports here are not CPU addresses, and there is no 'ranges' property in 6 LPC device node. 7 8Required properties: 9- compatible: value should be as follows: 10 (a) "hisilicon,hip06-lpc" 11 (b) "hisilicon,hip07-lpc" 12- #address-cells: must be 2 which stick to the ISA/EISA binding doc. 13- #size-cells: must be 1 which stick to the ISA/EISA binding doc. 14- reg: base memory range where the LPC register set is mapped. 15 16Note: 17 The node name before '@' must be "isa" to represent the binding stick to the 18 ISA/EISA binding specification. 19 20Example: 21 22isa@a01b0000 { 23 compatible = "hisilicon,hip06-lpc"; 24 #address-cells = <2>; 25 #size-cells = <1>; 26 reg = <0x0 0xa01b0000 0x0 0x1000>; 27 28 ipmi0: bt@e4 { 29 compatible = "ipmi-bt"; 30 device_type = "ipmi"; 31 reg = <0x01 0xe4 0x04>; 32 }; 33}; 34