1NXP i.MX System Controller Firmware (SCFW) 2-------------------------------------------------------------------- 3 4The System Controller Firmware (SCFW) is a low-level system function 5which runs on a dedicated Cortex-M core to provide power, clock, and 6resource management. It exists on some i.MX8 processors. e.g. i.MX8QM 7(QM, QP), and i.MX8QX (QXP, DX). 8 9The AP communicates with the SC using a multi-ported MU module found 10in the LSIO subsystem. The current definition of this MU module provides 115 remote AP connections to the SC to support up to 5 execution environments 12(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces 13with the LSIO DSC IP bus. The SC firmware will communicate with this MU 14using the MSI bus. 15 16System Controller Device Node: 17============================================================ 18 19The scu node with the following properties shall be under the /firmware/ node. 20 21Required properties: 22------------------- 23- compatible: should be "fsl,imx-scu". 24- mbox-names: should include "tx0", "tx1", "tx2", "tx3", 25 "rx0", "rx1", "rx2", "rx3"; 26 include "gip3" if want to support general MU interrupt. 27- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for 28 rx, and 1 optional MU channel for general interrupt. 29 All MU channels must be in the same MU instance. 30 Cross instances are not allowed. The MU instance can only 31 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need 32 to make sure use the one which is not conflict with other 33 execution environments. e.g. ATF. 34 Note: 35 Channel 0 must be "tx0" or "rx0". 36 Channel 1 must be "tx1" or "rx1". 37 Channel 2 must be "tx2" or "rx2". 38 Channel 3 must be "tx3" or "rx3". 39 General interrupt rx channel must be "gip3". 40 e.g. 41 mboxes = <&lsio_mu1 0 0 42 &lsio_mu1 0 1 43 &lsio_mu1 0 2 44 &lsio_mu1 0 3 45 &lsio_mu1 1 0 46 &lsio_mu1 1 1 47 &lsio_mu1 1 2 48 &lsio_mu1 1 3 49 &lsio_mu1 3 3>; 50 See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml 51 for detailed mailbox binding. 52 53Note: Each mu which supports general interrupt should have an alias correctly 54numbered in "aliases" node. 55e.g. 56aliases { 57 mu1 = &lsio_mu1; 58}; 59 60i.MX SCU Client Device Node: 61============================================================ 62 63Client nodes are maintained as children of the relevant IMX-SCU device node. 64 65Power domain bindings based on SCU Message Protocol 66------------------------------------------------------------ 67 68This binding for the SCU power domain providers uses the generic power 69domain binding[2]. 70 71Required properties: 72- compatible: Should be one of: 73 "fsl,imx8qm-scu-pd", 74 "fsl,imx8qxp-scu-pd" 75 followed by "fsl,scu-pd" 76 77- #power-domain-cells: Must be 1. Contains the Resource ID used by 78 SCU commands. 79 See detailed Resource ID list from: 80 include/dt-bindings/firmware/imx/rsrc.h 81 82Clock bindings based on SCU Message Protocol 83------------------------------------------------------------ 84 85This binding uses the common clock binding[1]. 86 87Required properties: 88- compatible: Should be one of: 89 "fsl,imx8qm-clock" 90 "fsl,imx8qxp-clock" 91 followed by "fsl,scu-clk" 92- #clock-cells: Should be 1. Contains the Clock ID value. 93- clocks: List of clock specifiers, must contain an entry for 94 each required entry in clock-names 95- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" 96 97The clock consumer should specify the desired clock by having the clock 98ID in its "clocks" phandle cell. 99 100See the full list of clock IDs from: 101include/dt-bindings/clock/imx8qxp-clock.h 102 103Pinctrl bindings based on SCU Message Protocol 104------------------------------------------------------------ 105 106This binding uses the i.MX common pinctrl binding[3]. 107 108Required properties: 109- compatible: Should be one of: 110 "fsl,imx8qm-iomuxc", 111 "fsl,imx8qxp-iomuxc", 112 "fsl,imx8dxl-iomuxc". 113 114Required properties for Pinctrl sub nodes: 115- fsl,pins: Each entry consists of 3 integers which represents 116 the mux and config setting for one pin. The first 2 117 integers <pin_id mux_mode> are specified using a 118 PIN_FUNC_ID macro, which can be found in 119 <dt-bindings/pinctrl/pads-imx8qm.h>, 120 <dt-bindings/pinctrl/pads-imx8qxp.h>, 121 <dt-bindings/pinctrl/pads-imx8dxl.h>. 122 The last integer CONFIG is the pad setting value like 123 pull-up on this pin. 124 125 Please refer to i.MX8QXP Reference Manual for detailed 126 CONFIG settings. 127 128[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 129[2] Documentation/devicetree/bindings/power/power-domain.yaml 130[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt 131 132RTC bindings based on SCU Message Protocol 133------------------------------------------------------------ 134 135Required properties: 136- compatible: should be "fsl,imx8qxp-sc-rtc"; 137 138OCOTP bindings based on SCU Message Protocol 139------------------------------------------------------------ 140Required properties: 141- compatible: Should be one of: 142 "fsl,imx8qm-scu-ocotp", 143 "fsl,imx8qxp-scu-ocotp". 144- #address-cells: Must be 1. Contains byte index 145- #size-cells: Must be 1. Contains byte length 146 147Optional Child nodes: 148 149- Data cells of ocotp: 150 Detailed bindings are described in bindings/nvmem/nvmem.txt 151 152Watchdog bindings based on SCU Message Protocol 153------------------------------------------------------------ 154 155Required properties: 156- compatible: should be: 157 "fsl,imx8qxp-sc-wdt" 158 followed by "fsl,imx-sc-wdt"; 159Optional properties: 160- timeout-sec: contains the watchdog timeout in seconds. 161 162SCU key bindings based on SCU Message Protocol 163------------------------------------------------------------ 164 165Required properties: 166- compatible: should be: 167 "fsl,imx8qxp-sc-key" 168 followed by "fsl,imx-sc-key"; 169- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml 170 171Thermal bindings based on SCU Message Protocol 172------------------------------------------------------------ 173 174Required properties: 175- compatible: Should be : 176 "fsl,imx8qxp-sc-thermal" 177 followed by "fsl,imx-sc-thermal"; 178 179- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml 180 for a description. 181 182Example (imx8qxp): 183------------- 184aliases { 185 mu1 = &lsio_mu1; 186}; 187 188lsio_mu1: mailbox@5d1c0000 { 189 ... 190 #mbox-cells = <2>; 191}; 192 193firmware { 194 scu { 195 compatible = "fsl,imx-scu"; 196 mbox-names = "tx0", "tx1", "tx2", "tx3", 197 "rx0", "rx1", "rx2", "rx3", 198 "gip3"; 199 mboxes = <&lsio_mu1 0 0 200 &lsio_mu1 0 1 201 &lsio_mu1 0 2 202 &lsio_mu1 0 3 203 &lsio_mu1 1 0 204 &lsio_mu1 1 1 205 &lsio_mu1 1 2 206 &lsio_mu1 1 3 207 &lsio_mu1 3 3>; 208 209 clk: clk { 210 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 211 #clock-cells = <1>; 212 }; 213 214 iomuxc { 215 compatible = "fsl,imx8qxp-iomuxc"; 216 217 pinctrl_lpuart0: lpuart0grp { 218 fsl,pins = < 219 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 220 SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 221 >; 222 }; 223 ... 224 }; 225 226 ocotp: imx8qx-ocotp { 227 compatible = "fsl,imx8qxp-scu-ocotp"; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 231 fec_mac0: mac@2c4 { 232 reg = <0x2c4 8>; 233 }; 234 }; 235 236 pd: imx8qx-pd { 237 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 238 #power-domain-cells = <1>; 239 }; 240 241 rtc: rtc { 242 compatible = "fsl,imx8qxp-sc-rtc"; 243 }; 244 245 scu_key: scu-key { 246 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 247 linux,keycodes = <KEY_POWER>; 248 }; 249 250 watchdog { 251 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 252 timeout-sec = <60>; 253 }; 254 255 tsens: thermal-sensor { 256 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 257 #thermal-sensor-cells = <1>; 258 }; 259 }; 260}; 261 262serial@5a060000 { 263 ... 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_lpuart0>; 266 clocks = <&clk IMX8QXP_UART0_CLK>, 267 <&clk IMX8QXP_UART0_IPG_CLK>; 268 clock-names = "per", "ipg"; 269 power-domains = <&pd IMX_SC_R_UART_0>; 270}; 271